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m68hc08 microcontrollers freescale.com mc68hc908gt16 mc68hc908gt8 mc68hc08gt16 data sheet mc68hc908gt16 rev. 5.0 04/2007

mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 2007. all rights reserved. mc68hc908gt16 mc68hc908gt8 mc68hc08gt16 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com
revision history mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 4 freescale semiconductor the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history (sheet 1 of 2) date revision level description page number(s) march, 2002 n/a original release n/a may, 2002 1.0 7.2 features ? corrected third bulleted item to reflect 4 percent variability 77 figure 15-1. forced monitor mode (low) ? reworked for clarity 211 figure 15-2. forced monitor mode (high) ? reworked for clarity 211 figure 15-3. standard monitor mode ? reworked for clarity 212 table 15-1. monitor mode signal requirements and options ? reworked for clarity 214 figure 12-4. port a i/o circuit ? reworked to corre ct pullup resistor 143 figure 12-11. port c i/o circuit ? reworked to correct pullup resistor 148 figure 12-15. port d i/o circuit ? reworked to correct pullup resistor 151 june, 2002 2.0 figure 2-2. control, status, and data registers ? corrected esci arbiter data register (sciadat) to reflect read-only status 50 figure 14-19. esci arbiter control register (sciactl) ? corrected address location designator from $0018 to $000a 170 figure 14-20. esci arbiter data register (sciadat) ? corrected address location designator from $0019 to $000b 171 september, 2004 3.0 (continued on next page) reformatted to meet current publications standards throughout 1.5.6 adc reference pins (v refh and v refl ) ? corrected connections 27 2.6.3 flash page erase operation ? updated procedure 41 2.6.4 flash mass erase operation ? updated procedure 42 2.6.5 flash program/read operation ? updated procedure 43 2.6.6 flash block protection ? description updated for clarity 45 3.3.5 conversion ? updated for clarity 52 3.6.3 adc voltage reference high pin (v refh ) ? corrected connections 53 3.6.4 adc voltage reference low pin (v refl ) ? corrected connections 53 3.7.1 adc status and control register ? updated description of the coco bit 54 chapter 4 configuration register (config) ? updated cop tmeout selections 57, 59 chapter 4 configuration register (config) ? updted ssrec bit usage 60 chapter 5 computer operating properly (cop) module ? updated timeout selections 62 figure 5-1. cop block diagram ? updated illustration for clarity 61 table 6-1. instruction set summary ? updated definitions for stop and wait 70 figure 7-9. code example for switching clock sources ? replaced example code 89 figure 7-10. code example for enabling the clock monitor ? replaced example code 90 figure 14-18. esci prescaler register (scpsc) ? corrected address location 172
revision history mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 5 september, 2004 3.0 (continued from previous page) chapter 15 system integration module (sim) ? clarified sim features and functionality 179, 182, 183, 184 15.7.2 sim reset status register ? clarified srsr operation 194 table 19-1. monitor mode signal requirements and options ? reworked 247 19.2.1 functional description ? co rrected break description 237, 240 19.3 monitor module (mon) ? reworked 243 chapter 20 electrical specific ations ? revised/added tables: 20.5 5.0-v dc electrical characteristics 20.6 3.0-v dc electrical characteristics 20.7 supply current characteristics 20.8 5-v control timing 20.9 3-v control timing 257 258 259 260 260 20.20 memory characteristics ? updated memory table 273 chapter 20 electrical specifications ? added figures: figure 20-1. rst and irq timing figure 20-2. rst and irq timing 260 260 march, 2006 4.0 appendix a mc68hc08gt16 ? introduces the mc68hc08gt16, the rom part equivalent to the mc68hc908gt16. 281 april, 200 7 5.0 4.2 functional description ? in the description of the cop rate select bit corrected the values for cop timeout period 57 figure 5-1. cop block diagram ? replaced busclkx4 with copclk 61 14.9.1 esci arbiter control register ? replaced one half with one quarter in definition for aclk = 0 176 14.9.3 bit time measurement ? replaced one half with one quarter in definition for aclk = 0 177 revised the following diagrams: figure 19-10. forced monitor mode (low) figure 19-11. forced monitor mode (high) figure 19-12. stan dard monitor mode 245 245 246 revision history (sheet 2 of 2) date revision level description page number(s)
revision history mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 6 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 7 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 3 analog-to-digital co nverter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 4 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 5 computer operating properly (cop) module . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 6 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 7 internal clock gene rator (icg) module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 chapter 8 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 9 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 chapter 10 low-voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 chapter 11 low-power modes (mo des). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 12 input/output (i/o) po rts (ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 chapter 13 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 chapter 14 enhanced serial commun ications interface (esci) modu le . . . . . . . . . . . . . 149 chapter 15 system integration module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 16 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 chapter 17 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 chapter 18 timer interface modul e (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 chapter 19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 chapter 20 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 chapter 21 ordering information and mechanical specifications . . . . . . . . . . . . . . . . . . 275 appendix a mc68hc08gt16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
list of chapters mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 8 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 9 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2.1 standard features of the mc68hc908gt16/mc68hc908gt8 . . . . . . . . . . . . . . . . . . . . . 21 1.2.2 features of the cpu08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.1 power supply pins (v dd and v ss ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.2 oscillator pins (pte4/osc1 and pte3/osc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.3 external reset pin (rst ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.5 adc and icg power supply pins (v dda and v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.6 adc reference pins (v refh and v refl ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.7 port a input/output (i/o) pins (pta7/kbd7 ?pta0/kbd0 ) . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.8 port b i/o pins (ptb7/ad7?ptb0/ad0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.9 port c i/o pins (ptc6?ptc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 1.5.10 port d i/o pins (ptd7/t2ch1?ptd0/ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.11 port e i/o pins (pte4?pte2, pte1/rxd, and pte0/t xd) . . . . . . . . . . . . . . . . . . . . . . . . . 28 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.2 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.3 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.4 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.5 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6.6 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.7 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.8 icg user trim registers (icgtr5 and icgtr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.9 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6.10 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 10 freescale semiconductor chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.2 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.3 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.4 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.5 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.6 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.1 adc analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.2 adc analog ground pin (v ssa ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.4 adc voltage reference low pin (v refl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.6.5 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.7.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 4 configuration register (config) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 5 computer operating properly (cop) module 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.1 copclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.5 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.6 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.8 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 11 5.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 chapter 6 central processor unit (cpu) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 chapter 7 internal clock gener ator (icg) module) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.1 clock enable circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2 internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.3.2.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2.2 modulo n divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2.3 frequency comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.3.2.4 digital loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.3.3 external clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3.3.1 external oscillator amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3.3.2 external clock input path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.4 clock monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.4.1 clock monitor reference generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.3.4.2 internal clock activity detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.4.3 external clock activity detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.5 clock selection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.5.1 clock selection switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3.5.2 clock switching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 12 freescale semiconductor 7.4 usage notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4.1 switching clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.2 enabling the clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.4.3 using clock monitor interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.4 quantization error in dco output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.4.1 digitally controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.4.2 binary weighted divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.4.3 variable-delay ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.4.4 ring oscillator fine-adjust circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.5 switching internal clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.6 nominal frequency settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.6.1 settling to within 15 percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6.2 settling to within 5 percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.6.3 total settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.7 trimming frequency on the internal clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6 config2 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6.1 external clock enable (extclken) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6.2 external crystal enable (extxtalen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.6.3 slow external clock (extslow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.4 oscillator enable in stop (oscenin stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.7 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.7.1 icg control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.7.2 icg multiplier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.7.3 icg trim register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.7.4 icg dco divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.7.5 icg dco stage register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 chapter 8 external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 chapter 9 keyboard interrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 13 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 chapter 10 low-voltage inhibit (lvi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 10.3.4 lvi trip selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 chapter 11 low-power modes (modes) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.1.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.1.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.2 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.4 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.5 internal clock generator module (icg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 11.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.6 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.7 external interrupt module (irq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 14 freescale semiconductor 11.8 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.9 low-voltage inhibit module (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.10 enhanced serial communications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.11 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.12 timer interface module (tim1 and tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.12.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.12.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.13 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.14 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.15 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 chapter 12 input/output (i/o) ports (ports) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.2.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 12.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.4.3 port c input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.5 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.5.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.5.2 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.5.3 port d input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.6 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.6.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.6.2 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 15 chapter 13 resets and interrupts 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2.3 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.2.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.2.3.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.2.3.3 low-voltage inhibit reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.3.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.3.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.2.4 sim reset status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.3.2 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.3.2.1 software interrupt (swi) instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.3.2.2 break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3.2.3 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3.2.4 internal clock generator (icg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 44 13.3.2.5 timer interface module 1 (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3.2.6 timer interface module 2 (tim2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3.2.7 serial peripheral interface (spi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3.2.8 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.3.2.9 kbd0 ?kbd7 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.3.2.10 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.3.2.11 timebase module (tbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.3.3 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.3.3.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.3.3.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.3.3.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 chapter 14 enhanced serial communications interface (esci) module 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 14.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 16 freescale semiconductor 14.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.6 esci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 62 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.7.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.7.2 pte1/rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.8.1 esci control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.8.2 esci control register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.8.3 esci control register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.8.4 esci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.8.5 esci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.8.6 esci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.8.7 esci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.8.8 esci prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.9 esci arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.9.1 esci arbiter control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.9.2 esci arbiter data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.9.3 bit time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.9.4 arbitration mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 chapter 15 system integrati on module (sim) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.2.2 clock startup from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 15.3.2.6 monitor mode entry module reset (modrst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 17 15.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 15.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.5.1.3 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.7.1 sim break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.7.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 chapter 16 serial peripheral interface (spi) module 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.3.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.3.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.4 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.4.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1 16.4.2 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.4.3 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 16.4.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.5 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.6.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.6.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.8 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.9 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.10 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.11.1 miso (master in/slave out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.11.2 mosi (master out/slave in). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.11.3 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.11.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 18 freescale semiconductor 16.12 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.12.1 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.12.2 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.12.3 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 chapter 17 timebase module (tbm) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.4 timebase register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 17.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 chapter 18 timer interface module (tim) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 18.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 18.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 26 18.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.4.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 18.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 18.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 18.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 18.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 18.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.7 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.9 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 18.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 31 18.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 18.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 18.9.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 18.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 19 chapter 19 development support 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 19.2.1.2 tim1 and tim2 during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 19.2.1.3 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 40 19.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 19.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 19.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 19.2.2.3 sim break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 19.2.2.4 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 19.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 19.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 19.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 19.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 19.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 19.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 19.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 chapter 20 electrical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 20.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.5 5.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 20.6 3.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 20.8 5-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.9 3-v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.10 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.11 external oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.12 trimmed accuracy of the internal clock generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 20.12.1 2.7-volt to 3.3-volt trimmed internal clock gener ator characteristics . . . . . . . . . . . . . . . 262 20.12.2 4.5-volt to 5.5-volt trimmed internal clock gener ator characteristics . . . . . . . . . . . . . . . 262 20.13 output high-voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 20.14 output low-voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 20.15 typical supply currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.16 adc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.17 5.0-v spi characteri stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
table of contents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 20 freescale semiconductor 20.18 3.0-v spi characteri stics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 20.19 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 20.20 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 chapter 21 ordering information and m echanical specifications 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.3 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 appendix a mc68hc08gt16 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 a.2 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 a.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 a.4 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 a.5 icg trim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 a.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 a.7 adc reference pins (v refh and v refl ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 a.8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 a.8.1 5.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 85 a.8.2 3.0-v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 86 a.8.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 a.9 adc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 a.9.1 internal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 a.9.2 memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 a.10 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 21 chapter 1 general description 1.1 introduction the mc68hc908gt16, mc68hc908gt8, and mc68hc08gt16 are members of the low-cost, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a vari ety of modules, memory sizes and types, and package types. all references to the mc68hc908gt16 in this data book apply equally to the mc68hc908gt8, unless otherwise stated. this revision introduces the mc68hc08gt16, the rom part equivalent to the mc68hc908gt16. the entire data book applies to this rom dev ice, with the exceptions outlined in appendix a mc68hc08gt16 . 1.2 features for convenience, features have been organized to reflect: ? standard features of the mc68hc908gt16/mc68hc908gt8 ? features of the cpu08 1.2.1 standard f eatures of the mc 68hc908gt16/mc68hc908gt8 ? high-performance m68hc08 architecture optimized for c-compilers ? fully upward-compatible object code wi th m6805, m146805, and m68hc05 families ? 8-mhz internal bus frequency ? internal oscillator requiring no external components: ? software selectable bus frequencies ? 25 percent accuracy with trim capability to 4 percent ? clock monitor ? option to allow use of external clock source or external crystal/ceramic resonator ? flash program memory security (1) ? on-chip programming firmware for use with hos t personal computer which does not require high voltage for entry ? in-system programming (isp) 1. no security feature is absolutely secure. however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
general description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 22 freescale semiconductor ? system protection features: ? optional computer operating properly (cop) reset ? low-voltage detection with optional reset and selectable trip points for 3.0-v and 5.0-v operation ? illegal opcode detection with reset ? illegal address detection with reset ? low-power design; fully static with stop and wait modes ? standard low-power modes of operation: ? wait mode ? stop mode ? master reset pin and power-on reset (por) ? 16 kbytes of on-chip 100k cycle write/er ase capable flash memory (8 kbytes on mc68hc908gt8) ? 512 bytes of on-chip random-access memory (ram) ? 720 bytes of flash programming routines rom ? serial peripheral interface module (spi) ? serial communications interface module (sci) ? two 16-bit, 2-channel timer interface modules (tim1 and tim2) with selectable input capture, output compare, and pulse-width mo dulation (pwm) capability on each channel ? 8-channel, 8-bit successive approximati on analog-to-digital converter (adc) ? break module (brk) to allow single breakpoint setting during in-circuit debugging ? internal pullups on irq and rst to reduce customer system cost ? up to 36 general-purpose input/output (i/o) pins, including: ? 28 shared-function i/o pins ? six or eight dedicated i/o pins, depending on package choice ? selectable pullups on inputs only on ports a, c, and d. selection is on an i ndividual port bit basis. during output mode, pullups are disengaged. ? high current 10-ma sink/10-ma sour ce capability on all port pins ? higher current 20-ma sink/source capability on ptc0?ptc4 ? timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source durin g stop mode for periodic wakeup from stop using an external 32-khz crystal or internal oscillator ? user selection of having the oscillator enabled or disabled during stop mode ? 8-bit keyboard wakeup port ? available packages: ? 42-pin shrink dual in-line package (sdip) ? 44-pin quad flat pack (qfp) ? specific features of the mc68hc908gt16 in 42-pin sdip are: ? port c is only 5 bits: ptc0?ptc4 ? port d is 8 bits: ptd0?ptd7; dual 2-channel tim modules ? specific features of the mc68hc908gt16 in 44-pin qfp are: ? port c is 7 bits: ptc0?ptc6 ? port d is 8 bits: ptd0?ptd7; dual 2-channel tim modules
mcu block diagram mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 23 1.2.2 features of the cpu08 features of the cpu08 include: ? enhanced hc05 programming model ? extensive loop control functions ? 16 addressing modes (eight more than the hc05) ? 16-bit index register and stack pointer ? memory-to-memory data transfers ? fast 8 8 multiply instruction ? fast 16/8 divide instruction ? binary-coded decimal (bcd) instructions ? optimization for controller applications ? efficient c language support 1.3 mcu block diagram figure 1-1 shows the structure of the mc68hc908gt16.
general description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 24 freescale semiconductor figure 1-1. mcu block diagram single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
pin assignments mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 25 1.4 pin assignments figure 1-2. 42-pin sdip pin assignments 21 22 ptd5/t1ch1 ptd4/t1ch0 ptb1/ad1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 ptb0/ad0 ptd7/t2ch1 v ss ptd3/spsck ptd2/mosi rst irq ptd0/ss ptd1/miso pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 pta5/kbd5 pta6/kbd6 pta7/kbd7 ptb6/ad6 ptb7/ad7 ptb3/ad3 ptb4/ad4 ptb5/ad5 v ssa (adc/icg) v dda (adc/icg) v refh (adc) v refl (adc) pte2 pte3/osc2 pte4/osc1 ptc0 ptc1 ptc2 ptc3 ptc4 pte0/txd pte1/rxd ptb2/ad2 20 23 ptd6/t2ch0 v dd pins not available on 42-pin package internal connection ptc5 connected to ground ptc6 connected to ground
general description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 26 freescale semiconductor figure 1-3. 44-pin qfp pin assignments 1.5 pin functions descriptions of the pin functions are provided here. 1.5.1 power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. th e mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 1-4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 33 32 31 30 29 28 27 26 25 24 23 rst pte0/txd pte1/rxd irq ptc0 ptc1 ptc2 ptc3 ptc4 ptc5 ptc6 ptd5/t1ch1 ptd4/t1ch0 v dd v ss ptd3/spsck ptd2/mosi ptd1/miso ptd0/ss ptd6/t2ch0 ptd7/t2ch1 ptb0/ad0 ptb6/ad6 ptb7/ad7 v refh v refl pta0/kbd0 ptb2/ad2 ptb3/ad3 ptb1/ad1 ptb4/ad4 ptb5/ad5 pta4/kbd4 pta5/kbd5 v dda pte4/osc1 pte3/osc2 pte2 v ssa pta1/kbd1 pta6/kbd6 pta7/kbd7 pta3/kbd3 pta2/kbd2 44 34 13 12 21 22
pin functions mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 27 figure 1-4. power supply bypassing 1.5.2 oscillator pins (pte4/osc1 and pte3/osc2) pte4/osc1 and pte3/osc2 are general-purpose, bidirect ional i/o port pins. these pins can also be programmed to be the connections for an external crystal, resonator or clock circuit. see chapter 7 internal clock generator (icg) module) . 1.5.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor. see chapter 15 system integration module (sim). 1.5.4 external interrupt pin (irq ) irq is an asynchronous external interrupt pin. th is pin contains an internal pullup resistor. see chapter 8 external interrupt (irq). 1.5.5 adc and icg power supply pins (v dda and v ssa ) v dda and v ssa are the power supply pins for the analog-to-dig ital converter (adc) and the internal clock generator (icg). connect the v dda pin to the same voltage potential as v dd , and the v ssa pin to the same voltage potential as v ss . decoupling of these pins should be as per the digital supply. see chapter 3 analog-to-digital converter (adc) and chapter 7 internal clock generator (icg) module). 1.5.6 adc reference pins (v refh and v refl ) v refh and v refl are the reference voltage pins for the analog-to-digital converter (adc). v refh is the high reference supply for the adc and should be filtered. v refh must be connected to the same voltage potential as the analog supply pin, v dda . v refl is the low reference supply for the adc and should be externally filtered. v refl must be connected to the same voltage potential as the analog supply pin v ssa . see chapter 3 analog-to-digital converter (adc) . mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown r epresent typical applications.
general description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 28 freescale semiconductor 1.5.7 port a input/out put (i/o) pins (pta7/kbd7 ?pta0/kbd0 ) pta7?pta0 are general-purpose, bidirectional i/o port pins. any or all of the port a pins can be programmed to serve as keyboard interrupt pins. see chapter 12 input/output (i/o) ports (ports) and chapter 9 keyboard interrupt module (kbi) . these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.5.8 port b i/o pi ns (ptb7/ad7?ptb0/ad0) ptb7?ptb0 are general-purpose, bidirectional i/o por t pins that can also be used for analog-to-digital converter (adc) inputs. see chapter 12 input/output (i/o) ports (ports) and chapter 3 analog-to-digital converter (adc) . 1.5.9 port c i/o pins (ptc6?ptc0) ptc6?ptc0 are general-purpose, bidirectional i/o port pins. ptc0?ptc4 have higher current sink/source capability. ptc5 and ptc6 are only available on the 44-pin qfp package. these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. see chapter 12 input/output (i/o) ports (ports) . 1.5.10 port d i/o pins (ptd7/t2ch1?ptd0/ss ) ptd7?ptd0 are special-function, bidirectional i/o port pins. ptd0?ptd3 can be programmed to be serial peripheral interface (spi) pins, while ptd4?ptd7 can be indi vidually programmed to be timer interface module (tim1 and tim2) pins. see chapter 18 timer interface module (tim) , chapter 16 serial peripheral interface (spi) module , and chapter 12 input/output (i/o) ports (ports) . these port pins also have selectable pullups when configured for input mode. the pullups are disengaged when configured for output mode. the pullups are selectable on an individual port bit basis. 1.5.11 port e i/o pins (pte4? pte2, pte1/rxd, and pte0/txd) pte0?pte4 are general-purpose, bidirectional i/o port pins. pte0?pte1 can also be programmed to be serial communications interface (sci) pins. see chapter 14 enhanced serial communications interface (esci) module and chapter 12 input/output (i/o) ports (ports) . pte3 and pte4 can also be programmed to be clock or oscillator pins. see chapter 4 configuration register (config) and chapter 12 input/output (i/o) ports (ports) . note any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports do not require termination, termination is recommended to reduce the possibility of static damage.
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 29 chapter 2 memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: ? user flash memory: ? mc68hc908gt16 ? 15,872 bytes ? mc68hc908gt8 ? 7,680 bytes ? 512 bytes of random-access memory (ram) ? 720 bytes of flash programming routines read-only memory (rom) ? 36 bytes of user-defined vectors ? 304 bytes of monitor rom 2.2 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved loca tions are marked with the word reserved or with the letter r. 2.4 input/output (i/o) section most of the control, status, and data registers ar e in the zero page area of $0000?$003f. additional i/o registers have these addresses: ? $fe00; sim break status register, sbsr ? $fe01; sim reset status register, srsr ? $fe02; reserved, subar ? $fe03; sim break flag control register, sbfcr ? $fe04; interrupt status register 1, int1 ? $fe05; interrupt status register 2, int2 ? $fe06; interrupt status register 3, int3 ? $fe07; reserved ? $fe08; flash control register, flcr ? $fe09; break address register high, brkh ? $fe0a; break address register low, brkl ? $fe0b; break status and control register, brkscr
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 30 freescale semiconductor ? $fe0c; lvi status register, lvisr ? $ff7e; flash block protect register, flbpr ? $ff80; icg user trim register 5v icgtr5 ? $ff81; icg user trim register 3v icgtr3 ? $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. $0000 i/o registers 64 bytes $003f $0040 ram 512 bytes $023f $0240 unimplemented 6416 bytes $1b4f $1b50 flash programming routines rom 720 bytes $1e1f $1e20 unimplemented 41,440 bytes $bfff $c000 flash memory mc68hc908gt16 15,872 bytes reserved (1) $c000 $dfff flash memory mc68hc908gt8 7,680 bytes $e000 $fdff $fdff $fe00 sim break status register (sbsr) 1. inadvertent access to these locations will not cause an illegal address reset. $fe01 sim reset status register (srsr) $fe02 reserved (subar) $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) figure is continued on the next page figure 2-1. memory map
input/output (i/o) section mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 31 $fe0c lvi status register (lvisr) $fe0d unimplemented 3 bytes $fe0f $fe10 unimplemented 16 bytes reserved for compatibility with monitor code for a-family part $fe1f $fe20 monitor rom 304 bytes $ff4f $ff50 unimplemented 46 bytes $ff7d $ff7e flash block protect register (flbpr) $ff7f unimplemented 1 byte $ff80 icg user trim register 5v (icgtr5) $ff81 icg user trim register 3v (icgtr3) $ff82 unimplemented 90 bytes $ffdb $ffdc flash vectors 36 bytes $ffff (2) 2. $fff6?$fffd reserved for eight security bytes figure 2-1. memory map (continued)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 32 freescale semiconductor addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 126. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 128. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 130. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register ( ptd) see page 132. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 126. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 128. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 130. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 133. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 135. read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 esci prescaler register (scpsc) see page 172. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 $000a esci arbiter control register (sciactl) see page 176. read: am1 alost am0 aclk afin arun aovfl ard8 write: reset:00000000 $000b esci arbiter data register (sciadat) see page 177. read: ard7 ard6 ard5 ar d4 ard3 ard2 ard1 ard0 write: reset:00000000 $000c data direction register e (ddre) see page 136. read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 7)
input/output (i/o) section mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 33 $000d port a input pullup enable register (ptapue) see page 127. read: ptapue7 ptapue6 ptapue5 ptapu e4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 131. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 134. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $0010 spi control register (spcr) see page 213. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 214. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 216. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 esci control register 1 (scc1) see page 163. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 esci control register 2 (scc2) see page 165. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 esci control register 3 (scc3) see page 167. read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 esci status register 1 (scs1) see page 168. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 esci status register 2 (scs2) see page 170. read: bkf rpf write: reset:00000000 $0018 esci data register (scdr) see page 171. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 esci baud rate register (scbr) see page 171. read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 7)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 34 freescale semiconductor $001a keyboard status and control register (intkbscr) see page 111. read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 112. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c timebase module control register (tbcr) see page 218. read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 $001d irq status and control register (intscr) see page 104. read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 $001e configuration register 2 (config2) ? see page 58. read: r 0 ext- xtalen ext-slow ext- clken 0 oscenin- stop r write: reset:00000000 $001f configuration register 1 (config1) ? see page 58. read: coprs lvistop lvirstd lvipwrd lvi5or3 (1) ssrec stop copd write: reset:00000000 1. one-time writable register after each reset, except lv i5or3 bit. lvi5or3 bit is only reset via por (power-on reset). $0020 timer 1 status and control register (t1sc) see page 231. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) see page 232. read: bit 7 654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) see page 233. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) see page 233. read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 7)
input/output (i/o) section mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 35 $0026 timer 1 channel 0 register high (t1ch0h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) see page 234. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) see page 231. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $002c timer 2 counter register high (t2cnth) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) see page 232. read: bit 7 654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) see page 233. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) see page 233. read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 timer 2 channel 0 register low (t2ch0l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 7)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 36 freescale semiconductor $0033 timer 2 channel 1 status and control register (t2sc1) see page 234. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $0036 icg control register (icgcr) see page 98. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 reset:00001000 $0037 icg multiplier register (icgmr) see page 99. read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 $0038 icg trim register (icgtr) see page 100. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 icg divider control register (icgdvr) see page 100. read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu $003a icg dco stage control register (icgdsr) see page 100. read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset: unaffected by reset $003b reserved read: rrrrrrrr write: reset: indeterminate after reset $003c adc status and control register (adscr) see page 54. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 $003d adc data register (adr) see page 55. read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 $003e adc clock register (adclk) see page 56. read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 $003f unimplemented read: write: reset: addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 7)
input/output (i/o) section mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 37 $fe00 sim break status register (sbsr) see page 242. read: rrrrrr sbsw r write: note reset:00000000 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 140. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 sim upper byte address register (subar) read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) see page 242. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 147. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 147. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 147. read: 000000if16if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: reset:00000000 $fe08 flash control register (flcr) see page 41. read: 0000 hven mass erase pgm write: reset:00000000 $fe09 break address register high (brkh) see page 241. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 241. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 241. read: brke brka 000000 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 7)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 38 freescale semiconductor $fe0c lvi status register (lvisr) see page 115. read: lviout 0000000 write: reset:00000000 $ff7e flash block protect register (flbpr) (1) see page 45. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset $ff80 icg user trim register 5v (icgtr5) (1) see page 46. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset: unaffected by reset $ff81 icg user trim register 3v (icgtr3) (1) see page 46. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset: unaffected by reset $ffff cop control register (copctl) see page 63. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset 1. n on-volatile flash register addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 7)
input/output (i/o) section mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 39 . table 2-1. vector addresses vector priority vector address vector lowest if16 $ffdc timebase vector (high) $ffdd timebase vector (low) if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) if12 $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) if11 $ffe6 sci error vector (high) $ffe7 sci error vector (low) if10 $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) if9 $ffea spi receive vector (high) $ffeb spi receive vector (low) if8 $ffec tim2 overflow vector (high) $ffed tim2 overflow vector (low) if7 $ffee tim2 channel 1 vector (high) $ffef tim2 channel 1 vector (low) if6 $fff0 tim2 channel 0 vector (high) $fff1 tim2 channel 0 vector (low) if5 $fff2 tim1 overflow vector (high) $fff3 tim1 overflow vector (low) if4 $fff4 tim1 channel 1 vector (high) $fff5 tim1 channel 1 vector (low) if3 $fff6 tim1 channel 0 vector (high) $fff7 tim1 channel 0 vector (low) if2 $fff8 icg vector (high) $fff9 icg vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 40 freescale semiconductor 2.5 random-access memory (ram) addresses $0040 through $023f are ram locations. t he location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and us er data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instru ctions can efficiently access all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 flash memory this sub-section describes the o peration of the embedded flash memory. this memory can be read, programmed, and erased from a single external supply. the program, erase, and read operations are enabled through the use of an internal charge pump. 2.6.1 functional description the flash memory is an array of 15,872 bytes (7,680 bytes on mc68hc908gt8) with an additional 36 bytes of user vectors, one byte of block pr otection and two bytes of icg user trim storage. an erased bit reads as 1 and a programmed bit reads as a 0 . memory in the flash array is organized into two rows per page basis. the page size is 64 bytes per page and the row size is 32 bytes per row. hence the minimum erase page size is 64 bytes and the minimum program row size is 32 bytes. program and erase operation operations are facilitated through control bits in flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: ? $c000?$fdff; user memory ($e000?$fdff on mc68hc908gt8) ?$fe08 ; flash control register ? $ff7e; flash block protect register ?$ff80 ; icg user trim register (icgtr5) ?$ff81 ; icg user trim register (icgtr3) ? $ffdc?$ffff; these locations are reserved for user-defined interrupt and reset vectors
flash memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 41 2.6.2 flash control register the flash control register (flcr) cont rols flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the 16 kbyte flash array for mass erase operation. 1 = mass erase operation selected 0 = mass erase operation unselected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 2.6.3 flash p age erase operation use the following procedure to erase a page (64 bytes) of flash memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80, or $xxc0. the 36-byte user interrupt vectors area also forms a page. any fl ash memory page can be erased alone. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr)
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 42 freescale semiconductor 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t erase (minimum 1 ms or 4 ms). 7. clear the erase bit. 8. wait for a time, t nvh (minimum 5 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. caution a page erase of the vector page will erase the internal oscillator trim values at $ff80 and $ff81. in applications that require more than 1000 program /erase cycles, use the 4 ms page erase specification to get improved long-term reliability. any application can use this 4 ms page erase specification. however, in applications where a flash lo cation will be erased and reprogramme d less than 1000 times, and speed is important, use the 1 ms page erase spec ification to get a shorter cycle time. 2.6.4 flash mass erase operation use the following procedure to erase the entire flash memory to read as a 1: 1. set both the erase bit and the mass bi t in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t merase (minimum 4 ms). 7. clear the erase and mass bits. note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl (minimum 100 s). 9. clear the hven bit. 10. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be 1. when in monitor mode, with security sequence failed (see 19.3.2 security ), write to the flash block protect register instead of any flash address.
flash memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 43 performed in the order as shown, but other unrelated operations may occur between the steps. caution a mass erase will erase the internal oscillator trim values at $ff80 and $ff81. 2.6.5 flash progra m/read operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $xx60, $x x80, $xxa0, $xxc0, or $xxe0. use the following step-by-step procedure to program a row of flash memory figure 2-4 is a flowchart of the programming algorithm. note only bytes which are currently $ff may be programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range desired. 4. wait for a time, t nvs (minimum 10 s). 5. set the hven bit. 6. wait for a time, t pgs (minimum 5 s). 7. write data to the flash address being programmed (1) . 8. wait for time, t prog (minimum 30 s). 9. repeat step 7 and 8 until all desired bytes within the row are programmed. 10. clear the pgm bit (1) . 11. wait for time, t nvh (minimum 5 s). 12. clear the hven bit. 13. after time, t rcv (typical 1 s), the memory can be accessed in read mode again. note the cop register at location $ffff should not be written between steps 5-12, when the hven bit is set. since this register is located at a valid flash address, unpredictable behavior may occu r if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 20.20 memory characteristics . 1. the time between each flash address change, or the time bet ween the last flash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum.
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 44 freescale semiconductor figure 2-4. flash programming flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), must not exceed the maximum programming time, t prog max. or the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased.
flash memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 45 2.6.6 flash bl ock protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a bloc k of memory from unintentional erase or program operations due to system malfunction. this protection is done by using of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit when the flbpr is program with all 0?s, the entir e memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory, address ranges as shown in 2.6.7 flash block protect register . once the flbpr is programmed with a value other than $ff or $fe, any erase or program of the flbpr or the protected block of flash memory is prohibited. mass erase is disabled whenever any block is prot ected (flbpr does not equal $ff). the flbpr itself can be erased or programmed only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from reset into the monitor mode. 2.6.7 flash block protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect bits these eight bits represent bits [13:6] of a 16-bit memory address. bit 15 and bit 14 are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be $xx00, $xx40, $xx80, and $xxc0 (64 bytes page boundaries) within the flash memory. figure 2-6. flash block protect start address address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) 1 flbpr value 16-bit memory address 000000 start address of flash 1 block protect
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 46 freescale semiconductor 2.6.8 icg user trim r egisters (icgtr5 and icgtr3) the icg user trim register are two normal bytes of fl ash memory which are allocated for the user to store copies of the icg trim register (icgtr) value. icgtr5 is allocated for storage of the trim value when a 5-v supply is used, icgtr3 for storage of the trim value when a 3-v supply is used. representative trim values are programmed into these locations by freescale but they may be erased and reprogrammed by the user at any time. storage and retrieval of data in these registers is not automatic and must be performed programmatically. typically, these locations are progr ammed by the user during an in-system calibration procedure and one of them, depending on the application supply voltage, is subsequently used by the user?s initialization code to configure the icg each time following a reset. icgtr5 is used by the mc68hc908gt16 monitor rom program during its initialization sequence if monitor mode was entered while clocking from the icg. if the contents of icgtr5 are not $ff then the contents are copied to icgtr. note the contents of icgtr3 are not utilized by the monitor rom program. trim[7:0] ? icg trim factor bits these bits are copied by the monitor rom progr am following a reset, if monitor mode was entered while clocking from the icg and may be copied by t he user?s initialization code to the icg trim register (icgtr). table 2-2. examples of protect address ranges bpr[7:0] addresses of protect range $00 the entire flash memory is protected. $01 ( 0000 0001 )$ c 0 4 0 ( 1 100 0000 01 00 0000) ? $ffff $02 ( 0000 0010 )$ c 0 8 0 ( 1 100 0000 10 00 0000) ? $ffff $03 ( 0000 0011 ) $c0c0 (11 00 0000 11 00 0000) ? $ffff $04 ( 0000 0100 )$ c 1 0 0 ( 1 1 00 0001 00 00 0000) ? $ffff and so on... $fc ( 1111 1100 ) $ff00 (11 11 1111 00 00 0000) ? ffff $fd ( 1111 1101 ) $ff40 (11 11 1111 01 00 0000) ? $ffff flbpr and vectors are protected $fe ( 1111 1110 ) $ff80 (1 111 1111 10 00 0000) ? ffff vectors are protected $ff the entire flash memory is not protected. address: icgtr5, $ff80 and icgtr3, $ff81 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset: unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-7. icg user trim registers (icgtr5 and icgtr3)
flash memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 47 2.6.9 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be executed while per forming a program or erase operation on the flash, otherwise the operation will discontin ue, and the flash will be on standby mode. 2.6.10 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will disconti nue, and the flash will be on standby mode note standby mode is the power saving mode of the flash module in which all internal control signals to the flash are inactive and the current consumption of the flash is at a minimum.
memory mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 48 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 49 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the 8-bit analog-to-digital converter (adc). 3.2 features features of the adc module include: ? eight channels with multiplexed input ? linear successive approxi mation with monotonicity ? 8-bit resolution ? single or continuous conversion ? conversion complete flag or conversion complete interrupt ? selectable adc clock 3.3 functional description the adc provides eight pins for sampling external sources at pins ptb7/ad7?ptb0/ad0. an analog multiplexer allows the single adc converter to se lect one of eight adc channels as adc voltage in (v adin ). v adin is converted by the successive approximati on register-based analog-to-digital converter. when the conversion is completed, adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . 3.3.1 adc port i/o pins ptb7/ad7?ptb0/ad0 are general-purpose i/o (input/outpu t) pins that share with the adc channels. the channel select bits define which a dc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as gener al-purpose i/o. writes to the port register or data direction register (ddr) will not have any affect on the po rt pin that is selected by the adc. read of a port pin in use by the adc will return a 0.
analog-to-digital converter (adc) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 50 freescale semiconductor figure 3-1. block diagram highlighting adc block and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 51 figure 3-2. adc block diagram 3.3.2 adc port i/o pins ptb7/ad7?ptb0/ad0 are general-purpose i/o pins that share with the adc channels. the channel select bits define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o . writes to the port register or data direction register (ddr) will not have any affect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a logic 0. 3.3.3 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $ff (full scale). if the input voltage equals v refl , the adc converts it to $00. input voltages between v refh and v refl are a straight-line linear conversion. note the adc input voltage must always be greater than v ssa and less than v dda . v refh must always be greater than or equal to v refl . internal data bus read ddrbx write ddrbx reset write ptbx read ptbx ptbx ddrbx ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch4?adch0 adc data register aien coco disable disable adc channel x adiv2?adiv0 adiclk voltage in v refl v refh
analog-to-digital converter (adc) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 52 freescale semiconductor note connect the v dda pin to the same voltage potential as the v dd pin, and connect the v ssa pin to the same voltage potential as the v ss pin. the v dda pin should be routed carefully for maximum noise immunity. 3.3.4 conversion time conversion starts after a write to the adc status and control register (adscr). one conversion will take between 16 and 17 adc clock cycles. the adivx and ad iclk bits should be set to provide a 1-mhz adc clock frequency. 3.3.5 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be over written whether that data has been read or not. conversions will conti nue until the adco bit is cleared. the coco bit is set after the first conversion and will stay set until the next read of the adc data register. in single conversion mode, conversion begins with a write to t he adscr. only one conversion occurs between writes to the adscr. when a conversion is in process and the adscr is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.6 accuracy and precision the conversion process is monot onic and has no missing codes. 3.4 interrupts when the aien bit is set, the adc module is c apable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the co co bit is at 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 3.5 low-power modes the wait and stop instruction can put the mcu in low power-consumption standby modes. 3.5.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting ad ch4?adch0 bits in the adc status and control register before executing the wait instruction. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency
i/o signals mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 53 3.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. 3.6 i/o signals the adc module has eight pins shared with port b, ptb7/ad7?ptb0/ad0. 3.6.1 adc analog power pin (v dda ) the adc analog portion uses v dda as its power pin. connect the v dda pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v dda for good results. note for maximum noise immunity, route v dda carefully and place bypass capacitors as close as possible to the package. 3.6.2 adc analog ground pin (v ssa ) the adc analog portion uses v ssa as its ground pin. connect the v ssa pin to the same voltage potential as v ss . note route v ssa cleanly to avoid any offset errors. 3.6.3 adc voltage reference high pin (v refh ) the adc analog portion uses v refh as its upper voltage reference pin. the v refh pin must be connected to the same voltage potential as v dda . external filtering is often necessary to ensure a clean v refh for good results. any noise present on this pin will be reflected and possibly m agnified in a/d conversion values. note for maximum noise immunity, route v refh carefully and place bypass capacitors as close as possibl e to the package. routing v refh close and parallel to v refl may improve common mode noise rejection. 3.6.4 adc voltage reference low pin (v refl ) the adc analog portion uses v refl as its lower voltage reference pin. the v refl pin must be connected to the same voltage potential as v ssa . external filtering is often necessary to ensure a clean v refl for good results. any noise present on this pin will be reflected and possibly m agnified in a/d conversion values. note for maximum noise immunity, route v refl carefully and, if not connected to v ss , place bypass capacitors as cl ose as possible to the package. routing v refh close and parallel to v refl may improve common mode noise rejection.
analog-to-digital converter (adc) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 54 freescale semiconductor 3.6.5 adc voltage in (v adin ) v adin is the input voltage signal from one of the eight adc channels to the adc module. 3.7 i/o registers these i/o registers control and monitor adc operation: ? adc status and control register (adscr) ? adc data register (adr) ? adc clock register (adclk) 3.7.1 adc status and control register function of the adc status and control register (adscr) is described here. coco ? conversions complete bit in non-interrupt mode (aien = 0), coco is a read-only bit that is set at the end of each conversion. coco will stay set until cleared by a read of the adc data register. reset clears this bit. in interrupt mode (aien = 1), coco is a read-only bit that is not set at the end of a conversion. it always reads as a 0. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) or cpu interrupt enabled (aien = 1) note the write function of the coco bit is reserved. when writing to the adscr register, always have a 0 in the coco bit position. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: r reset:00011111 r= reserved figure 3-3. adc status and control register (adscr)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 55 adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to select one of 16 adc channels. only eight channels, ad7?ad0, are available on this mcu. the channels are detailed in table 3-1 . care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. see table 3-1. the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note recovery from the disabled state requi res one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes, as specified in table 3-1 , are used to verify the operation of the adc converter both in production test and for user applications. 3.7.2 adc data register one 8-bit result register, adc data register (adr), is provided. this register is updated each time an adc conversion completes. table 3-1. mux channel select (1) 1. if any unused channels are selected, the resulting adc conversion will be unknown or reserved. adch4 adch3 adch2 adch1 adch0 input select 00000 p t b 0 / a d 0 00001 p t b 1 / a d 1 00010 p t b 1 / a d 2 00011 p t b 2 / a d 3 00100 p t b 4 / a d 4 00101 p t b 5 / a d 5 00110 p t b 6 / a d 6 00111 p t b 7 / a d 7 0 1 1 1 0 1 0 0 0 0 reserved 11101 v refh 11110 v refl 1 1 1 1 1 adc power off address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 3-4. adc data register (adr)
analog-to-digital converter (adc) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 56 freescale semiconductor 3.7.3 adc clock register the adc clock register (adclk) selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2?adiv0 form a 3-bit field which selects the divi de ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurat ions. the adc clock should be set to approximately 1 mhz. adiclk ? adc input clock select bit adiclk selects either the bus clock or the oscill ator output clock (cgmxclk) as the input clock source to generate the internal adc clock. re set selects cgmxclk as the adc clock source. 1 = internal bus clock 0 = oscillator output clock (cgmxclk) the adc requires a clock rate of approximately 1 mhz for correct operation. if the selected clock source is not fast enough, the adc will generate incorrect conversions. see 20.16 adc characteristics . address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 = unimplemented figure 3-5. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1x (1) 1. x = don?t care x (1) adc input clock 16 f adic = f cgmxclk or bus frequency adiv[2:0] ? 1 mhz
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 57 chapter 4 configuration register (config) 4.1 introduction this section describes the configuration registers, config1 and config2. the configuration registers enable or disable these options: ? stop mode recovery time (32 cgmx clk cycles or 4096 cgmxclk cycles) ? cop timeout period (262,128 or 8176 copclk cycles) ?stop instruction ? computer operating properly module (cop) ? low-voltage inhibit (lvi) module control and voltage trip point selection ? enable/disable the oscillator (osc) during stop mode ? external clock, external crystal, or icg clock source 4.2 functional description the configuration registers are used in the initializatio n of various options. the c onfiguration registers can be written once after each reset. all of the configurat ion register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that these registers be written immediately after reset. the conf iguration registers are located at $001e and $001f and may be read at anytime. note on a flash device, the options except lvi5or3 are one-time writable by the user after each reset. the lvi5or3 bit is one-time writable by the user only after each por (power-on reset). the config registers are not in the flash memory but are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 4-1 and figure 4-2.
configuration register (config) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 58 freescale semiconductor extxtalen ? external crystal enable bit extxtalen enables the external oscillator circuits to be configured for a crystal configuration where the pte4/osc1 and pte3/osc2 pins are t he connections for an external crystal. clearing the extxtalen bit (default setting) a llows the pte3/osc2 pin to function as a general-purpose i/o pin. refer to table 4-1 for configuration options for the external source. see chapter 7 internal clock generator (icg) module) for a more detailed descript ion of the external clock operation. extxtalen, when set, also configures the clock moni tor to expect an external clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external clock stabilization divider in the clock monitor for a 4096-cycle timeout to allow the proper stabilization time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. 1 = allows pte3/osc2 to be an external crystal connection. 0 = pte3/osc2 functions as an i/o port pin (default). extslow ? slow external crystal enable bit the extslow bit has two functions. it configures the icg module for a fast (1 mhz to 8 mhz) or slow (30 khz to 100 khz) speed crystal. the option also configures the clock monitor operation in the icg module to expect an external fr equency higher (307.2 khz to 32 mhz) or lower (60 hz to 307.2 khz) than the base frequency of the internal oscillator. see chapter 7 internal clock generator (icg) module) . 1 = icg set for slow external crystal operation 0 = icg set for fast external crystal operation note this bit does not function without setting the extclken bit also. address: $001e bit 76 5 432 1 bit 0 read: 0 0 extxtalen extslow extclken 0 osceninstop r write: r e s e t :00000000 = unimplemented r = reserved figure 4-1. configuration register 2 (config2) address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd lvi5or3 ssrec stop copd write: reset:0000see note000 note: lvi5or3 bit is only reset via por (power-on reset) figure 4-2. configuration register 1 (config1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 59 extclken ? external clock enable bit extclken enables an external clock source or crystal /ceramic resonator to be used as a clock input. setting this bit enables pte4/osc1 pin to be a clock input pin. clearing this bit (default setting) allows the pte4/osc1 and pte3/osc2 pins to function as a general-purpose input/output (i/o) pin. refer to table 4-1 for configuration options for the external source. see chapter 7 internal clock generator (icg) module) for a more detailed description of the external clock operation. 1 = allows pte4/osc1 to be an external clock connection 0 = pte4/osc1 and pte3/osc2 function as i/o port pins (default). osceninstop ? oscillator enable in stop mode bit osceninstop, when set, will enable the internal clock generator module to continue to generate clocks (either internal, iclk, or external, eclk) in stop mode. see chapter 7 internal clock generator (icg) module) . this function is used to keep the timebase running while the rest of the microcontroller stops. see chapter 17 timebase module (tbm) . when clear, all clock generation will cease and both iclk and eclk will be forced low during stop mode. th e default state for this option is clear, disabling the icg in stop mode. 1 = oscillator enabled to operate during stop mode 0 = oscillator disabled during stop mode (default) note this bit has the same functionality as the oscstopenb config bit in mc68hc908gp32 and mc68hc908gr8 parts. coprs ? cop rate select bit copd selects the cop timeout period. reset clears coprs. see chapter 5 computer operating properly (cop) module 1 = cop timeout period = 8176 copclk cycles 0 = cop timeout period = 262,128 copclk cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see chapter 10 low-voltage inhibit (lvi) . 1 = lvi module resets disabled 0 = lvi module resets enabled table 4-1. external clock option settings external clock configuration bits pin function description extclken extxtalen pt e4/osc1 pte3/osc2 0 0 pte4 pte3 default setting ? external oscillator disabled 0 1 pte4 pte3 external oscillator di sabled since extclken not set 1 0 osc1 pte3 external oscillator configured for an external clock source input (square wave) on osc1 1 1 osc1 osc2 external oscillator configured for an external crystal configuration on osc1 and osc2. system will also operate with square-wave clock source in osc1.
configuration register (config) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 60 freescale semiconductor lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 10 low-voltage inhibit (lvi) . 1 = lvi module power disabled 0 = lvi module power enabled lvi5or3 ? lvi 5-v or 3-v operating mode bit lvi5or3 selects the voltage operating mode of the lvi module. see chapter 10 low-voltage inhibit (lvi) the voltage mode selected for the lvi should match the operating v dd . see chapter 20 electrical specifications for the lvi?s voltage trip points for each of the modes. 1 = lvi operates in 5-v mode. 0 = lvi operates in 3-v mode. note the lvi5or3 bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096-cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclck cycles note exiting stop mode by an lvi reset will result in the long stop recovery. the short stop recovery delay can be enabled when using the internal oscillator, a crystal, or a ceramic resonator and the osceninstop bit is set. the short stop recovery delay can be enabled when an external oscillator is used, regardless of the osceninstop setting. the short stop recovery delay must be disabled (ssrec = 0) when the osceninstop bit is cleared. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 5 computer operating properly (cop) module . 1 = cop module disabled 0 = cop module enabled
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 61 chapter 5 computer operating properly (cop) module 5.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the config register. 5.2 functional description figure 5-1 shows the structure of the cop module. figure 5-1. cop block diagram copctl write copclk reset vector fetch sim reset circuit reset status register internal reset sources sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter cop counter
computer operating properly (cop) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 62 freescale semiconductor the cop counter is a free-running 6-bit counter prec eded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 262,128 or 8176 copclk cycles, depending on the state of the cop rate select bit, coprs, in the configuration register. with a 8176 copclk cycle overflow option, a 32.768- khz crystal gives a cop timeout period of 250 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 copclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq1 is held at v tst . during the break state, v tst on the rst pin disables the cop. note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 5.3 i/o signals the following paragraphs describe the signals shown in figure 5-1 . 5.3.1 copclk copclk is a clock generated by the clock selection ci rcuit in the internal clock generator (icg). see 7.3.5 clock selection circuit for more details. 5.3.2 stop instruction the stop instruction clears the cop prescaler. 5.3.3 copctl write writing any value to the cop control register (copctl) (see 5.4 cop control register ) clears the cop counter and clears bits 12 through 5 of the prescaler. reading the cop control register returns the low byte of the reset vector. 5.3.4 powe r-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 5.3.5 internal reset an internal reset clears the cop prescaler and the cop counter.
cop control register mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 63 5.3.6 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. 5.3.7 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register. see chapter 4 configuration register (config). 5.3.8 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register. see chapter 4 configuration register (config). 5.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 5.5 interrupts the cop does not generate central processor unit (cpu) interrupt requests. 5.6 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is entered by having blank reset vectors and not having v tst on the irq pin, the cop is automatically disabled until a por occurs. 5.7 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 5.7.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 5-2. cop control register (copctl)
computer operating properly (cop) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 64 freescale semiconductor 5.7.2 stop mode stop mode turns off the copclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 5.8 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin.
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 65 chapter 6 central processor unit (cpu) 6.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.2 features features of the cpu include: ? object code fully upward-compatible with m68hc05 family ? 16-bit stack pointer with stack manipulation instructions ? 16-bit index register with x-re gister manipulation instructions ? 8-mhz cpu internal bus frequency ? 64-kbyte program/data memory space ? 16 addressing modes ? memory-to-memory data moves without using accumulator ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? enhanced binary-coded decimal (bcd) data handling ? modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes ? low-power stop and wait modes 6.3 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map.
central processor unit (cpu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 66 freescale semiconductor figure 6-1. cpu registers 6.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 6.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70
cpu registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 67 6.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc)
central processor unit (cpu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 68 freescale semiconductor 6.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr)
arithmetic/logic unit (alu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 69 z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.5.1 wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. ? disables the cpu clock 6.5.2 stop mode the stop instruction: ? clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 6.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted.
central processor unit (cpu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 70 freescale semiconductor 6.7 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. table 6-1. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc #opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add #opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediat e value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and #opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc re l br anch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bclr n, opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ??????rel 22 rr 3 c b0 b7 0 b0 b7 c
instruction set summary mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 71 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n ,opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n,opr ,rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? dir ( b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n,opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 6-1. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 72 freescale semiconductor clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp c omple ment (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx #opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
instruction set summary mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 73 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx #opr ldhx opr l oad h:x fro m m h:x ( m:m + 1 ) 0?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp l ogical shift le ft (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9ed a ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ps ha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 table 6-1. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0
central processor unit (cpu) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 74 freescale semiconductor pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pul l (pcl) inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m ( m:m + 1) (h:x) 0 ? ? ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i 0; stop processing ??0???inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 table 6-1. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 b0 b7 c
opcode map mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 75 6.8 opcode map see table 6-2 . swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ??????inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 wait enable interrupts; wait for interrupt i bit 0; inhibit cpu clocking until interrupted ??0???inh 8f 1 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offse t byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct des tination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit ? not affected table 6-1. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 76 freescale semiconductor central processor unit (cpu) table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3e x t 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 ls r x 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2i x 1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2d i r 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2i x 1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 77 chapter 7 internal clock generator (icg) module) 7.1 introduction the internal clock generator module (icg) is used to create a stable clock source for the microcontroller without using any external components. the icg gener ates the oscillator output clock (cgmxclk), which is used by the low-voltage inhibit (lvi) and other modules. the icg also generates the clock generator output (cgmout), which is fed to the system integration module (sim) to create the bus clocks. the bus frequency will be one-fourth the frequency of cgmxclk and one-half the frequency of cgmout. finally, the icg generates the timebase cl ock (tbmclk), which is used in the timebase module (tbm) and the computer operating properly (cop) clock (copclk) which is used by the cop module. 7.2 features the icg has these features: ? selectable external clock generator, either 1-pin ex ternal source or 2-pin crystal, multiplexed with port pins ? internal clock generator with programmable frequenc y output in integer multiples of a nominal frequency (307.2 khz 25 percent) ? frequency adjust (trim) regist er to improve variability to 4 percent ? bus clock software selectable from either intern al or external clock (bus frequency range from 76.8 khz 25 percent to 9.75 mhz 25 percent in 76.8-khz increments note do not exceed the maximum bus frequency of 8 mhz at 5.0 v and 4 mhz at 3.0 v. ? timebase clock automatically selected from external if external clock is available ? clock monitor for both internal and external clocks 7.3 functional description the icg, shown in figure 7-2 , contains these major submodules: ? clock enable circuit ? internal clock generator ? external clock generator ? clock monitor circuit ? clock selection circuit
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 78 freescale semiconductor figure 7-1. block diagram highlighting icg module and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 79 figure 7-2. icg module block diagram internal to mcu external external clock generator extclken extxtalen pte4 logic pte3 logic ecgs osc1 pte4 osc2 pte3 internal clock generator osceninstop simoscen ibase icgs cmon clock monitor circuit eclk iclk clock selection circuit eoff ioff cgmxclk cs cgmout extslow clock/pin enable circuit icgon ecgon ecgen icgen dstg[7:0] tbmclk reset ddiv[3:0] ficgs name name name config2 register bit register bit module signal n[6:0} trim[7:0] name top level signal copclk
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 80 freescale semiconductor 7.3.1 clock enable circuit the clock enable circuit is used to enable the internal clock (iclk) or external clock (eclk) and the port logic which is shared with the oscillator pins (o sc1 and osc2). the clock enable circuit generates an icg stop (icgstop) signal which stops all clocks (iclk, eclk, and the low-frequency base clock, ibase). icgstop is set and the icg is disabled in stop mode if the oscillator enable stop bit (osceninstop) in the config2 register is clear. the icg clocks will be enabled in stop mode if osceninstop is high. the internal clock enable signal (icgen) turns on th e internal clock generator which generates iclk. icgen is set (active) whenever the icgon bit is set and the icgstop signal is clear. when icgen is clear, iclk and ibase are both low. the external clock enable signal (ecgen) turns on the external clock generator which generates eclk. ecgen is set (active) whenever the ecgon bit is set and the icgstop signal is clear. ecgon cannot be set unless the external clock enable (extclken) bit in the config2 register is set. when ecgen is clear, eclk is low. the port e4 enable signal (pe4en) turns on the port e4 logic. since port e4 is on the same pin as osc1, this signal is only active (set) when the external clock function is not desired. therefore, pe4en is clear when ecgon is set. pe4en is not gated with icgstop, which means that if the ecgon bit is set, the port e4 logic will remain disabled in stop mode. the port e3 enable signal (pe3en) turns on the port e3 logic. since port e3 is on the same pin as osc2, this signal is only active (set) when 2-pin oscillator function is not desired. therefore, pe3en is clear when ecgon and the external crystal enable (extxtalen) bit in the config2 register are both set. pe3en is not gated with icgstop, which means that if ec gon and extxtalen are set, the port e3 logic will remain disabled in stop mode. 7.3.2 internal clock generator the internal clock generator, shown in figure 7-3 , creates a low frequency base clock (ibase), which operates at a nominal frequency (f nom ) of 307.2 khz 25 percent, and an internal clock (iclk) which is an integer multiple of ibase. this multiple is the icg multiplier factor (n), which is programmed in the icg multiplier register (icgmr). the internal clock generator is turned off and the output clocks (ibase and iclk) are held low when the internal clock generator enable signal (icgen) is clear. the internal clock generator contains: ? a digitally controlled oscillator ? a modulo n divider ? a frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators ? a digital loop filter
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 81 figure 7-3. internal clock generator block diagram 7.3.2.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccurate oscillator which generates the internal clock (iclk). the clock period of iclk is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of only a limited number of bits in ddiv and dstg, the precision of the output (iclk) is restricted to a precision of approximately 0.202 percent to 0.368 percent when measured over several cycles (of the desired frequency). additionally, since the propagat ion delays of the devices used in the dco ring oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require alternately running faster and slower than desir ed, making the worst case cycle-to-cycle frequency variation 6.45 percent to 11.8 percent (of the desired frequency). the valid values of ddiv:dstg range from $000 to $9ff. for more information on the quantization error in the dco, see 7.4.4 quantization error in dco output . 7.3.2.2 modulo n divider the modulo n divider creates the lo w-frequency base clock (i base) by dividing the internal clock (iclk) by the icg multiplier factor (n), contained in the ic g multiplier register (icgmr). when n is programmed to a $01 or $00, the divider is disabled and iclk is passed through to ibase undivided. when the internal clock generator is stable, the frequency of ibase will be equal to the nominal frequency (f nom ) of 307.2 khz 25 percent. digitally iclk trim[7:0] voltage and current references digital ++ + ? ? ? n[6:0] dstg[7:0] ficgs icgen ibase ddiv[3:0] loop filter controlled oscillator frequency comparator clock generator modulo n divider name name name config2 register bit register bit module signal name top level signal
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 82 freescale semiconductor 7.3.2.3 frequency comparator the frequency comparator effectiv ely compares the low-frequency base clock (ibase) to a nominal frequency, f nom . first, the frequency comparator converts ibase to a voltage by charging a known capacitor with a current reference for a period dependent on ibase. this voltage is compared to a voltage reference with comparators, whose outputs are fed to the digital loop filter. the dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to 25 percent error in f nom . 7.3.2.4 digital loop filter the digital loop filter (dlf) uses the outputs of the frequency comparator to adjust the internal clock (iclk) clock period. the dlf generates the dco divider control bits (ddiv[3:0]) and the dco stage control bits (dstg[7:0]), which are fed to t he dco. the dlf first concatenates the ddiv and dstg registers (ddiv[3:0]:dstg[7:0]) and then adds or subtracts a value dependent on the relative error in the low-frequency base clock?s period, as shown in table 7-1 . in some extreme error conditions, such as operating at a v dd level which is out of specification, the dlf may attempt to use a value above the maximum ($9ff) or below the minimum ($000). in both cases, the value for ddiv will be between $a and $f. in this range, the ddiv value will be interpret ed the same as $9 (the slowest condition). recovering from this condition requires subtracting (increasing frequency) in the normal fashion until the value is again below $9ff. (if the desired value is $9xx, the value may settle at $axx through $fxx. this is an acceptable operating condition.) if the error is less than 5 percent, the internal clock generator?s filter stable indicator (ficgs) is set, indicating rela tive frequency accuracy to the clock monitor. table 7-1. correction sizes from dlf to dco frequency error of ibase compared to f nom ddvi[3:0]:dstg[7:0] correction current to new ddiv[3:0]:dstg[7:0] (1) 1. x = maximum error is independent of value in ddiv[3:0]. ddi v increments or decrements when an addition to dstg[7:0] carries or borrows. relative correction in dco ibase < 0.85 f nom ?32 (?$020) minimum $xff to $xdf ?2/31 ?6.45% maximum $x20 to $x00 ?2/19 ?10.5% 0.85 f nom < ibase ibase < 0.95 f nom ?8 (?$008) minimum $xff to $xf7 ?0.5/31 ?1.61% maximum $x08 to $x00 ?0.5/17.5 ?2.86% 0.95 f nom < ibase ibase < f nom ?1 (?$001) minimum $xff to $xfe ?0.0625/31 ?0.202% maximum $x01 to $x00 ?0.0625/17.0625 ?0.366% f nom < ibase ibase < 1.05 f nom +1 (+$001) minimum $xfe to $xff +0.0625/30.9375 +0.202% maximum $x00 to $x01 +0.0625/17 +0.368% 1.05 f nom < ibase ibase < 1.15 f nom +8 (+$008) minimum $xf7 to $xff +0.5/30.5 +1.64% maximum $x00 to $x08 +0.5/17 +2.94% 1.15 f nom < ibase +32 (+$020) minimum $xdf to $xff +2/29 +6.90% maximum $x00 to $x20 +2/17 +11.8%
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 83 7.3.3 external clock generator the icg also provides for an external oscillator or external clock source, if desired. the external clock generator, shown in figure 7-4 , contains an external oscillator amplifier and an external clock input path. figure 7-4. external clock generator block diagram 7.3.3.1 external oscillator amplifier the external oscillator amplifier prov ides the gain required by an external crystal connected in a pierce oscillator configuration. the amount of this gain is controlled by the slow external (extslow) bit in the config2 register. when extslow is set, the amplifier gain is reduced for operating low-frequency crystals (32 khz to 100 khz). when extslow is clear , the amplifier gain will be sufficient for 1-mhz to 8-mhz crystals. extslow must be configured correctly for the given crystal or the circuit may not operate. the amplifier is enabled when the external clock generator enable (ecgen) signal is set and when the external crystal enable (extxtalen) bit in the conf ig2 register is set. ecgen is controlled by the clock enable circuit (see 7.3.1 clock enable circuit ) and indicates that the external clock function is desired. when enabled, the amplifier will be connected between the pte4/osc1 and pte3/osc2 pins. otherwise, the pte3/osc2 pin reverts to its port function. c 1 c 2 r b x 1 r s * ecgen extxtalen eclk internal to mcu external osc1 pte4 osc2 pte3 amplifier input path extslow name name name name config2 bit top level signal register bit module signal external clock generator *r s can be 0 (shorted) when used with higher- frequency crystals. refer to manufacturer?s data. these components are required for external crystal use only.
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 84 freescale semiconductor in its typical configuration, the external oscillator requires five external components: 1. crystal, x 1 2. fixed capacitor, c 1 3. tuning capacitor, c 2 (can also be a fixed capacitor) 4. feedback resistor, rb 5. series resistor, r s (included in figure 7-4 to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information.) 7.3.3.2 external clock input path the external clock input path is the means by which the microcontroller uses an external clock source. the input to the path is the pte4/osc1 pin and the out put is the external cloc k (eclk). the path, which contains input buffering, is enabled when the external clock generator enable signal (ecgen) is set. when not enabled, the pte4/osc1 pin reverts to its port function. 7.3.4 clock m onitor circuit the icg contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (eclk) and the internal clock (iclk) to dete rmine if either clock source has been corrupted. the clock monitor circuit, shown in figure 7-5 , contains these blocks: ? clock monitor reference generator ? internal clock activity detector ? external clock activity detector 7.3.4.1 clock monitor reference generator the clock monitor uses a reference based on one clock source to monitor the other clock source. the clock monitor reference generator generates the extern al reference clock (eref) based on the external clock (eclk) and the internal reference clock (iref) based on the internal clock (iclk). to simplify the circuit, the low-frequency base clock (ibase) is used in place of iclk bec ause it always operates at or near 307.2 khz. for proper operation, eref must be at least twice as slow as ibase and iref must be at least twice as slow as eclk. to guarantee that iref is slower than eclk and er ef is slower than ibase, one of the signals is divided down. which signal is divided and by how much is determined by the external slow (extslow) and external crystal enable (extxtalen) bits in the config2 register, according to the rules in table 7-2 . note each signal (ibase and eclk) is always divided by four. a longer divider is used on either ibase or eclk based on the extslow bit.
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 85 figure 7-5. clock monitor block diagram to conserve size, the long divider (divide by 4096) is al so used as an external cr ystal stabilization divider. the divider is reset when the external clock generator is turned off or in stop mode (ecgen is clear). when the external clock generator is first turned on, the external clock generator stable bit (ecgs) will be clear. this condition automatically selects eclk as the input to the long divider. the external stabilization clock (estbclk) will be eclk divided by 16 when extxtalen is low or 4096 when extxtalen is high. this timeout allows the crystal to stabilize. the falling edge of estbclk is used to set ecgs, which will set after a full 16 or 4096 cycles. when ecgs is set, the divider returns to its normal function. estbclk may be generated by either ibase or eclk, but any clocking will only reinforce the set condition. if ecgs is cleared because the clock monitor determined that eclk was inactive, the divider will revert to a stabilizati on divider. since this will change the er ef and iref divide ratios, it is important to turn the clock monitor off (cmon = 0) a fter inactivity is detected to ensure valid recovery. extxtalen extslow ficgs ioff cmon ficgs ibase icgen eref ioff icgs ibase extxtalen extslow ecgs eclk ecgen icgon eref estbclk iref estbclk iref ecgen eclk cmon ecgs eoff cmon eoff ecgs icgs ibase icgen eclk ecgen iclk activity detector reference generator eclk activity detector name name name config2 register bit register bit module signal name top level signal
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 86 freescale semiconductor 7.3.4.2 internal clock activity detector the internal clock activity detector, shown in figure 7-6 , looks for at least one falling edge on the low-frequency base clock (ibase) every time the external reference (eref) is low. since eref is less than half the frequency of ibase, this should occur every time. if it does not occur two consecutive times, the internal clock inactivity indicator (ioff) is set. ioff will be cleared the next time there is a falling edge of ibase while eref is low. figure 7-6. internal clock activity detector the internal clock stable bit (icgs) is also generated in the internal clock activi ty detector. icgs is set when the internal clock generator?s filter stable si gnal (ficgs) indicates that ibase is within about 5 percent of the target 307.2 khz 25 percent for two consecutive meas urements. icgs is cleared when ficgs is clear, the internal clock generator is turned off or is in stop mode (icgen is clear), or when ioff is set. 7.3.4.3 external clock activity detector the external clock activity detector, shown in figure 7-7 , looks for at least one falling edge on the external clock (eclk) every time the internal reference (iref) is low. since iref is less than half the frequency of eclk, this should occur every time. if it does not occur two consecutive times, the external clock inactivity indicator (eoff) is set. eo ff will be cleared the next time there is a falling edge of eclk while iref is low. the external clock stable bit (ecgs) is also generated in the external clock activity detector. ecgs is set on a falling edge of the external stabilization clock (estbclk). this will be 4096 eclk cycles after the external clock generator on bit is set, or the mcu exits stop mode (ecgen = 1) if the external crystal enable (extxtalen) in the config2 register is set, or 16 cycles when extxtalen is clear. ecgs is cleared when the external clock generator is turned off or in stop mode (ecgen is clear) or when eoff is set. icgs ioff ibase r dq ck dffrr r icgen r d ck dffrs s q ck q 1/4 r ficgs eref cmon r dq ck dffrr r name name name name config2 register bit top level signal register bit module signal dlf measure output clock
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 87 figure 7-7. external clock activity detector 7.3.5 clock se lection circuit the clock selection circuit, shown in figure 7-8 , contains two clock switches which generate the oscillator output clock (cgmxclk) and the timebase clock (tbmclk) from either the internal clock (iclk) or the external clock (eclk). the cop clock (copclk) is i dentical to tbmclk. the clock selection circuit also contains a divide-by-two circuit which creates the clock generator output clock (cgmout), which generates the bus clocks. figure 7-8. clock selection circuit block diagram eggs eoff eclk r d q ck dffrr r estbclk r d ck dffrs s q ck q 1/4 r ecgen iref cmon name name name name config2 register bit top level signal register bit module signal iclk eclk ioff eoff force_i force_e select output iclk eclk ioff eoff force_i force_e select output reset eclk eoff ecgon iclk ioff v ss cs div2 name name name name config2 register bit top level signal register bit module signal synchronizing clock switcher synchronizing clock switcher cgmout cgmxclk tbmclk copclk
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 88 freescale semiconductor 7.3.5.1 clock selection switches the first switch creates the oscillator output clock (cgm xclk) from either the internal clock (iclk) or the external clock (eclk), based on the clock select bi t (cs; set selects eclk, clear selects iclk). when switching the cs bit, both iclk and eclk must be on (icgon and ecgon set). the clock being switched to also must be stable (icgs or ecgs set). the second switch creates the timebase clock (tbmclk) and the cop clock (copclk) from iclk or eclk based on the external clock on bit. when ecgon is set, the switch automatically selects the external clock, regardless of the state of the ecgs bit. 7.3.5.2 clock switching circuit to robustly switch between the internal clock (iclk) and the external clock (eclk), the switch assumes the clocks are completely asynchr onous, so a synchronizing circuit is required to make the transition. when the select input (the clock select bit for the oscillator output clock switch or the external clock on bit for the timebase clock switch) is changed, the switch will continue to operate off the original clock for between one and two cycles as the select input is transitioned through one side of the synchronizer. next, the output will be held low for between one and two cycles of the new clock as the select input transitions through the other side. then the output starts swit ching at the new clock?s frequency. this transition guarantees that no glitches will be seen on the output even though the select input may change asynchronously to the clocks. the unpredictably of the transition period is a necessary result of the asynchronicity. the switch automatically selects iclk during reset. when the clock monitor is on (cmon is set) and it determines one of the clock sources is inactive (as indicated by the ioff or eoff signals), the circuit is forced to select the active clock. there are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected. however, the active side will not be selected until one to two clock cycles after the ioff or eoff signal transitions. 7.4 usage notes the icg has several features which can provide protection to the microcontroller if properly used. other features can greatly simplify usage of the icg if ce rtain techniques are employed. this section describes several possible ways to use the icg and its features. these techniques are not the only ways to use the icg and may not be optimum for all environments. in any case, these techniques should be used only as a template, and the user should modify them according to the application?s requirements. these notes include: ? switching clock sources ? enabling the clock monitor ? using clock monitor interrupts ? quantization error in digitally controlled oscillator (dco) output ? switching internal clock frequencies ? nominal frequency settling time ? improving frequency settling time ? trimming frequency
usage notes mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 89 7.4.1 switchin g clock sources ? switching from one clock source to another requi res both clock sources to be enabled and stable. a simple flow requires: ? enable desired clock source ? wait for it to become stable ? switch clocks ? disable previous clock source the key point to remember in this flow is that th e clock source cannot be switched (cs cannot be written) unless the desired clock is on and stable. a short assembly code example of how to employ this flow is shown in figure 7-9 . ;* clock switching code example ;* this code switches from internal to external clock ;* clock monitor and interrupts are not enabled ;* icg clock switch switchitoe: bset ecgon,icgcr ; turn on external oscillator brclr ecgs,icgcr,* ; wait until external clock engaged bset cs,icgcr ; select external clock for bus bclr icgon,icgcr ; turn off internal clock (if desired) figure 7-9. code example for switching clock sources 7.4.2 enabling the clock monitor many applications require the clock monitor to dete rmine if one of the clock sources has become inactive, so the other can be used to recover from a poten tially dangerous situation. using the clock monitor requires both clocks to be active (ecgon and icgon both set). to enable the clock monitor, both clocks also must be stable (ecgs and icgs both set). this is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable. enabling the clock monitor and clock monitor in terrupts requires a flow similar to this: ? enable the alternate clock source ? wait for both clock sources to be stable ? switch to the desired clock source if necessary ? enable the clock monitor ? enable clock monitor interrupts these events must happen in sequence. a short assembly code example of how to employ this flow is shown in figure 7-10 .
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 90 freescale semiconductor ;* clock monitor enable code example ;* this code turns on both clocks, selects the desired one, ;* then turns on the clock monitor and cm interrupt ;* icg clock monitor enable cmenable: bset ecgon,icgcr ; turn on external oscillator ; (assumes internal osc is on) brclr ecgs,icgcr,* ; wait until external clock engaged bset cs,icgcr ; select external clock for bus bset cmon,icgcr ; enable clock monitor bset cmie,icgcr ; enable cm interrupt figure 7-10. code example for enabling the clock monitor 7.4.3 using clock monitor interrupts the clock monitor circuit can be used to recover from perilous situations such as crystal loss. to use the clock monitor effectively, t hese points should be observed: ? enable the clock monitor and clock monitor interrupts. ? the first statement in the clock monitor interrupt service routine (cmisr) should be a read to the icg control register (icgcr) to verify that the cloc k monitor flag (cmf) is set. this is also the first step in clearing the cmf bit. ? the second statement in the cmisr should be a wr ite to the icgcr to clear the cmf bit (write the bit low). writing the bit high will not affect it. this statement does not n eed to immediately follow the first, but must be contained in the cmisr. ? the third statement in the cmisr should be to clear the cmon bit. this is required to ensure proper reconfiguration of the reference dividers. this statement also must be contained in the cmisr. ? although the clock monitor can be enabled only when bo th clocks are stable (icgs is set or ecgs is set), it will remain set if o ne of the clocks goes unstable. ? the clock monitor only works if the external slow (extslow) bit in the config2 register is set to the correct value. ? the internal and external clocks must both be enabled and running to use the clock monitor. ? when the clock monitor detects inactivity, the inac tive clock is automatically deselected and the active clock selected as the source for cgmx clk and tbmclk. the cmisr can use the state of the cs bit to check which clock is inactive. ? when the clock monitor detects inactivity, t he application may have been subjected to extreme conditions which may have affected other circuits. the cmisr should take any appropriate precautions. 7.4.4 quantization error in dco output the digitally controlled oscillator (dco) is comprised of three major sub-blocks: 1. binary weighted divider 2. variable-delay ring oscillator 3. ring oscillator fine-adjust circuit each of these blocks affects the clock period of the in ternal clock (iclk). since these blocks are controlled by the digital loop filter (dlf) outputs ddiv and dstg, the output of the dco can change only in
usage notes mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 91 quantized steps as the dlf increments or decrements its output. the following sections describe how each block will affect the output frequency. 7.4.4.1 digitally controlled oscillator the digitally controlled oscillator (dco) is an inaccurate oscillator which generates the internal clock (iclk), whose clock period is dependent on the digital loop filter outputs (dstg[7:0] and ddiv[3:0]). because of the digital nature of the dco, the clock period of iclk will change in quantized steps. this will create a clock period difference or quantization e rror (q-err) from one cycle to the next. over several cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202 percent to 0.368 percent. the dependence of this error on the ddiv[3:0] value and the number of cycles the error is measured over is shown in table 7-2 . 7.4.4.2 binary weighted divider the binary weighted divider divides the output of the ring oscillator by a power of two, specified by the dco divider control bits (ddiv[3:0]). ddiv maximizes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. when ddiv is %0000, the ring oscillator?s output is divided by 1. incrementing ddiv by one will double the period; decrementing ddiv will halve the period. the dlf cannot directly increment or decrement ddiv; ddiv is only incremented or decremented when an addition or subtraction to dstg carries or borrows. 7.4.4.3 variable-delay ring oscillator the variable-delay ring oscill ator?s period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three dco stage control bits (dstg[7:5]). a dstg[7:5] of %000 corresponds to 17 stage delays; dstg[7:5] of %111 corresponds to 31 stage delays. adjusting the dstg[5] bit has a 6.45 percent to 11.8 percent effect on the output frequency. this also corresponds to the size correction made when the frequency error is greater than 15 percent. the value of the binary weighted divider does not affect the relative change in output clock period for a given change in dstg[7:5]. table 7-2. quantization error in iclk ddiv[3:0] iclk cycles bus cycles iclk q-err %0000 (min) 1 na 6.45%?11.8% %0000 (min) 4 1 1.61%?2.94% %0000 (min) 32 8 0.202%?0.368% %0001 1 na 3.23%?5.88% %0001 4 1 0.806%?1.47% %0001 16 4 0.202%?0.368% %0010 1 na 1.61%?2.94% %0010 4 1 0.403%?0.735% %0010 8 2 0.202%?0.368% %0011 1 na 0.806%?1.47% %0011 4 1 0.202%?0.368% %0100 1 na 0.403%?0.735% %0100 2 1 0.202%?0.368% %0101?%1001 (max) 1 1 0.202%?0.368%
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 92 freescale semiconductor 7.4.4.4 ring oscillator fine-adjust circuit the ring oscillator fine-adjust ci rcuit causes the ring oscillator to effectively operate at non-integer numbers of stage delays by operating at two different points for a variable number of cycles specified by the lower five dco stage control bits (dstg[4:0]). for example: ? when dstg[7:5] is %011, the ring oscilla tor nominally operates at 23 stage delays. ? when dstg[4:0] is %00000, the ring will always operate at 23 stage delays. ? when dstg[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles. ? likewise, when dstg[4:0] is %11111, the ring oper ates at 25 stage delays for 31 of 32 cycles and at 23 stage delays for one of 32 cycles. ? when dstg[7:5] is %111, similar results are achiev ed by including a variable divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles. adjusting the dstg[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period. this corresponds to the minimum size correction made by the dlf, and the inherent, long-term quantization error in the output frequency. 7.4.5 switching in ternal clock frequencies the frequency of the internal clock (iclk) may need to be changed for some applications. for example, if the reset condition does not provide the correct freq uency, or if the clock is slowed down for a low-power mode (or sped up after a low-power mode), the freq uency must be changed by programming the internal clock multiplier factor (n). the frequency of iclk is n times the frequency of ibase, which is 307.2 khz 25 percent. before switching frequencies by changing the n val ue, the clock monitor must be disabled. this is because when n is c hanged, the frequency of the low-freq uency base clock (ibase) will change proportionally until the digital loop filter has corrected the error. since the clock monitor uses ibase, it could erroneously detect an inactive clock. the clock monitor cannot be re-enabled until the internal clock is stable again (icgs is set). the following flow is an example of how to change the clock frequency: ? verify there is no clock monitor interrupt by reading the cmf bit. ? turn off the clock monitor. ? if desired, switch to the external clock (see 7.4.1 switching clock sources ). ? change the value of n. ? switch back to internal (see 7.4.1 switching clock sources ), if desired. ? turn on the clock monitor (see 7.4.2 enabling the clock monitor ), if desired. 7.4.6 nominal fr equency settling time because the clock period of the internal clock (iclk) is dependent on the digital loop filter outputs (ddiv and dstg) which cannot change instantaneously, iclk temporarily will operate at an incorrect clock period when any operating condition changes. this happens whenever the part is reset, the icg multiply factor (n) is changed, the icg trim factor (trim) is c hanged, or the internal clock is enabled after inactivity (stop mode or disabled operation). the time that the iclk takes to adjust to the correct period is known as the settling time.
usage notes mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 93 settling time depends primarily on how many corrections it takes to change the clock period and the period of each correction. since the corrections r equire four periods of the low-frequency base clock (4* ibase ), and since iclk is n (the icg multiply factor for the desired frequency) times faster than ibase, each correction takes 4*n* iclk . the period of iclk, however, will vary as the corrections occur. 7.4.6.1 settling to within 15 percent when the error is greater than 15 percent, the filter takes eight corrections to double or halve the clock period. due to how the dco increases or decreases the clock period, the total period of these eight corrections is approximately 11 times the period of the fastest correction. (if the corrections were perfectly linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly nonlinear.) therefore, the total time it takes to double or halve the clock period is 44*n* iclkfast . if the clock period needs more than doubled or halved, the same relationship applies, only for each time the clock period needs doubled, the total number of cycl es doubles. that is, when transitioning from fast to slow, going from the initial speed to half speed takes 44*n* iclkfast ; from half speed to quarter speed takes 88*n* iclkfast ; going from quarter speed to eighth speed takes 176*n* iclkfast ; and so on. this series can be expressed as (2 x ?1)*44*n* iclkfast , where x is the number of times the speed needs doubled or halved. since 2 x happens to be equal to iclkslow / iclkfast , the equation reduces to 44*n*( iclkslow ? iclkfast ). note that increasing speed takes much longer th an decreasing speed since n is higher. this can be expressed in terms of the initial clock period ( 1 ) minus the final clock period ( 2 ) as such: 7.4.6.2 settling to within 5 percent once the clock period is within 15 percent of the de sired clock period, the filter starts making smaller adjustments. when between 15 percent and 5 percent error, each correction will adjust the clock period between 1.61 percent and 2.94 percent. in this mode, a maximum of eight corrections will be required to get to less than 5 percent error. since the clock period is relatively close to desired, each correction takes approximately the same period of time, or 4* ibase . at this point, the internal clock stable bit (icgs) will be set and the clock frequency is usable, although the e rror will be as high as 5 percent. the total time to this point is: 7.4.6.3 total settling time once the clock period is within 5 percent of the desired clock period, the filter starts making minimum adjustments. in this mode, each correction will adjust the frequency between 0.202 percent and 0.368 percent. a maximum of 24 corrections will be required to get to the minimum error. each correction takes approximately the same period of time, or 4* ibase . added to the corrections for 15 percent to 5 percent, this makes 32 corrections (128* ibase ) to get from 15 percent to the minimum error. the total time to the minimum error is: the equations for 15 , 5 , and tot are dependent on the actual initial and final clock periods 1 and 2 , not the nominal. this means the variability in the ic lk frequency due to process, temperature, and voltage must be considered. additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. this means a worst case adjustment of up to 35 percent (iclk 15 abs 44n 1 2 ? () [] = 5 abs 44n 1 2 ? () [] 32 ibase + = tot abs 44n 1 2 ? () [] 128 ibase + =
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 94 freescale semiconductor clock period tolerance plus 10 percent) must be ad ded. this adjustment can be reduced with trimming. table 7-3 shows some typical values for settling time. 7.4.7 trimming frequency on the inter nal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, will vary as much as 25 percent due to process, temperature, and voltage dependencies. these dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. the method of changing the unadjusted operating point is by changing the size of the capacitor. this capacitor is designed with 639 equally sized units. of that number, 384 of these units are always connected. the remaining 255 units are put in by adjus ting the icg trim factor (trim). the default value for trim is $80, or 128 units, making the default c apacitor size 512. each unit added or removed will adjust the output frequency by about 0.195 percent of the unadjusted frequency (adding to trim will decrease frequency). theref ore, the frequency of ibase can be changed to 25 percent of its unadjusted value, which is enough to cancel the process variability mentioned before. the best way to trim the internal clock is to use th e timer to measure the width of an input pulse on an input capture pin (this pulse must be supplied by the application and should be as long or wide as possible). considering the prescale value of the timer and the theoretical (zero error) frequency of the bus (307.2 khz *n/4), the error can be calculated. this error, expressed as a percentage, can be divided by 0.195 percent and the resultant factor added or subtracted from trim. this process should be repeated to eliminate any residual error. 7.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 7.5.1 wait mode the icg remains active in wait mode. if enabled, the icg interrupt to the cpu can bring the mcu out of wait mode. in some applications, low power-consumption is desired in wait mode and a high-frequency clock is not needed. in these applications, reduce power consumpti on by either selecting a low-frequency external clock and turn the internal clock generator off or reduce the bus frequency by minimizing the icg multiplier factor (n) before executing the wait instruction. table 7-3. typical settling time examples 1 2 n 15 5 tot 1/ (6.45 mhz) 1/ (25.8 mhz) 84 430 s 535 s 850 s 1/ (25.8 mhz) 1/ (6.45 mhz) 21 107 s 212 s 525 s 1/ (25.8 mhz) 1/ (307.2 khz) 1 141 s 246 s 560 s 1/ (307.2 khz) 1/ (25.8 mhz) 84 11.9 ms 12.0 ms 12.3 ms
config2 options mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 95 7.5.2 stop mode the value of the oscillator enable in stop (oscenin stop) bit in the config2 register determines the behavior of the icg in stop mode. if osceninsto p is low, the icg is disabled in stop and, upon execution of the stop instruction, all icg activi ty will cease and the ou tput clocks (cgmxclk, cgmout, copclk, and tbmclk) w ill be held low. power consumption will be minimal. if osceninstop is high, the icg is enabled in stop and activity will continue. this is useful if the timebase module (tbm) is required to bring the mcu out of stop mode. icg interrupts will not bring the mcu out of stop mode in this case. during stop mode, if osceninstop is low, several fu nctions in the icg are affected. the stable bits (ecgs and icgs) are cleared, which will enable the external clock stabilization divider upon recovery. the clock monitor is disabled (cmon = 0) which will also clear the clock monitor interrupt enable (cmie) and clock monitor flag (cmf) bits. the cs, icgon , ecgon, n, trim, ddiv, and dstg bits are unaffected. 7.6 config2 options four config2 register options affect the functionality of the icg. these options are: 1. extclken, external clock enable 2. extxtalen, external crystal enable 3. extslow, slow external clock 4. osceninstop, oscillator enable in stop all config2 options will have a default setting. refer to chapter 4 configuration register (config) on how the config2 register is used. 7.6.1 external cl ock enable (extclken) external clock enable (extclken), when set, enables the ecgon bit to be set. ecgon turns on the external clock input path through the pte4/osc1 pin. when extclken is clear, ecgon cannot be set and pte4/osc1 will always perform the pte4 function. the default state for this option is clear. 7.6.2 external cryst al enable (extxtalen) external crystal enable (extxtalen), when set, will enable an amplifier to drive the pte3/osc2 pin from the pte4/osc1 pin. the amplifier will drive only if the external clock enable (extclken) bit and the ecgon bit are also set. if extclken or ecgon are clear, pte3/osc2 will perform the pte3 function. when extxtalen is clear, pte3/osc2 will always perform the pte3 function. extxtalen, when set, also configures the clock monitor to expect an exte rnal clock source in the valid range of crystals (30 khz to 100 khz or 1 mhz to 8 mhz). when extxtalen is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 hz to 32 mhz). extxtalen, when set, also configures the external cl ock stabilization divider in the clock monitor for a 4096 cycle timeout to allow the pr oper stabilization time for a crystal. when extxtalen is clear, the stabilization divider is configured to 16 cycles sinc e an external clock source does not need a startup time. the default state for this option is clear.
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 96 freescale semiconductor 7.6.3 slow external clock (extslow) slow external clock (extslow), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 khz?100 khz) if properly enabled with the external clock enable (extclken) and external crystal enable (extxtalen) bits. when clear, extslow enables high-frequency crystal operation (1 mhz to 8 mhz). extslow, when set, also configures the clock monitor to expect an external clock source that is slower than the low-frequency base clock (60 hz to 307.2 khz). when extslow is clear, the clock monitor will expect an external clock faster than the lo w-frequency base clock (307.2 khz to 32 mhz). the default state for this option is clear. 7.6.4 oscillator enable in stop (osceninstop) oscillator enable in stop (oscenin stop), when set, will enable the icg to continue to generate clocks (either cgmxclk, cgmout, copclk, or tbmclk) in stop mode. this function is used to keep the timebase and cop running while the rest of the microcontroller stops. the clock monitor and autoswitching functions remain operative. when osceninstop is clear, all clock generati on will cease and cgmxclk, cgmout, copclk, and tbmclk will be forced low during stop mode. the cl ock monitor and autoswitching functions become inoperative. the default state for this option is clear. 7.7 input/output (i/o) registers the icg contains five registers, summarized in figure 7-11 . these registers are: 1. icg control register (icgcr) 2. icg multiplier register (icgmr) 3. icg trim register (icgtr) 4. icg dco divider control register (icgdvr) 5. icg dco stage control register (icgdsr) several of the bits in these registers have interacti on where the state of one bit may force another bit to a particular state or prevent another bit from being set or cleared. a summary of this interaction is shown in table 7-4. addr.register name bit 7654321bit 0 $0036 icg control register (icgcr) see page 98. read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 1. see 7.7.1 icg control register for method of clearing the cmf bit. $0037 icg multiply register (icgmr) see page 99. read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 = unimplemented r = reserved u = unaffected figure 7-11. icg module i/o register summary
input/output (i/o) registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 97 $0038 icg trim register (icgtr) see page 100. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 icg divider control register (icgdvr) see page 100. read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu $003a icg dco stage control register (icgdsr) see page 100. read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset: unaffected by reset table 7-4. icg module register bit interaction summary condition register bit results for given condition cmie cmf cmon cs icgon icgs ecgon ecgs n[6:0] trim[7:0] ddiv[3:0] dstg[7:0] reset 00001000$15$80?? osceninstop = 0, stop = 1 000??0?0???? extclken = 0 00001?00??uwuw cmf = 1 ?(1)1?1?1?uwuwuwuw cmon = 0 0 0 (0)????? ? ? ?? cmon = 1 ??(1)?1?1?uwuwuwuw cs = 0 ???(0) 1 ??? ? ? uwuw cs = 1 ???(1)??1?? ??? icgon = 0 0001(0)01????? icgon = 1 ????(1)??? ? ? uwuw icgs = 0 us ? us uc ? (0) ? ? ? ? ? ? ecgon = 0 00001?(0)0??uwuw ecgs = 0 us?usus???(0) ? ? ?? ioff = 1 ? 1* (1) 1 (1) 0 (1) ? uw uw uw uw eoff = 1 ? 1* (1) 0 (1) ? (1) 0 uw uw uw uw n = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? trim = written (0) (0) (0) ? ? 0* ? ? ? ? ? ? ? register bit is unaffected by the given condition. 0, 1 register bit is forced clear or set (respectively) in the given condition. 0*, 1* register bit is temporarily forced clear or set (respectively) in the given condition. (0), (1) register bit must be clear or set (res pectively) for the given condition to occur. us, uc, uw register bit cannot be set, cleared, or written (respectively) in the given condition. addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 7-11. icg module i/o register summary (continued)
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 98 freescale semiconductor 7.7.1 icg c ontrol register the icg control register (icgcr) contains the contro l and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits. cmie ? clock monitor interrupt enable bit this read/write bit enables clock monitor interrupts. an interrupt will occur when both cmie and cmf are set. cmie can be set when the cmon bit has been set for at least one cycle. cmie is forced clear when cmon is clear or during reset. 1 = clock monitor interrupts enabled 0 = clock monitor interrupts disabled cmf ? clock monitor interrupt flag this read-only bit is set when the clock monitor determines that either iclk or eclk becomes inactive and the cmon bit is set. this bit is cleared by first re ading the bit while it is set, followed by writing the bit low. this bit is forced clear when cmon is clear or during reset. 1 = either iclk or eclk has become inactive. 0 = iclk and eclk have not become inactive since th e last read of the icgcr, or the clock monitor is disabled. cmon ? clock monitor on bit this read/write bit enables the clock monitor. cm on can be set when both iclk and eclk have been on and stable for at least one bus cycle. (icgon, ecgon, icgs, and ecgs are all set.) cmon is forced set when cmf is set, to avoid inadvertent clea ring of cmf. cmon is forced clear when either icgon or ecgon is clear, during stop mode with osceninstop low, or during reset. 1 = clock monitor output enabled 0 = clock monitor output disabled cs ? clock select bit this read/write bit determines which clock will generate the oscillator output clock (cgmxclk). this bit can be set when ecgon and ecgs have been set for at least one bus cycle and can be cleared when icgon and icgs have been set for at least one bus cycle. this bit is forced set when the clock monitor determines the internal clock (iclk) is inacti ve or when icgon is clear. this bit is forced clear when the clock monitor determines t hat the external clock (eclk) is inactive, when ecgon is clear, or during reset. 1 = external clock (eclk) sources cgmxclk 0 = internal clock (iclk) sources cgmxclk address: $0036 bit 7654321bit 0 read: cmie cmf cmon cs icgon icgs ecgon ecgs write: 0 (1) reset:00001000 1. see cmf bit description for method of clearing cmf bit. = unimplemented figure 7-12. icg control register (icgcr)
input/output (i/o) registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 99 icgon ? internal clock generator on bit this read/write bit enables the internal clock generator. icgon can be cleared when the cs bit has been set and the cmon bit has been clear for at least one bus cycle. icgon is forced set when the cmon bit is set, the cs bit is clear, or during reset. 1 = internal clock generator enabled 0 = internal clock generator disabled icgs ? internal clock generator stable bit this read-only bit indicates when the internal clock generator has determined that the internal clock (iclk) is within about 5 percent of the desired valu e. this bit is forced clear when the clock monitor determines the iclk is inactive , when icgon is clear, when the icg multiplier register (icgmr) is written, when the icg trim register (icgtr) is written, during stop mode with osceninstop low, or during reset. 1 = internal clock is within 5 percent of the desired value. 0 = internal clock may not be within 5 percent of the desired value. ecgon ? external clock generator on bit this read/write bit enables the external clock generator. ecgon can be cleared when the cs and cmon bits have been clear for at least one bus cycl e. ecgon is forced set when the cmon bit or the cs bit is set. ecgon is forced clear during reset. 1 = external clock generator enabled 0 = external clock generator disabled ecgs ? external clock generator stable bit this read-only bit indicates when at least 4096 external clock (eclk) cycles have elapsed since the external clock generator was enabled. this is not an assurance of the stability of eclk but is meant to provide a startup delay. this bit is forced clear when the clock monitor determines eclk is inactive, when ecgon is clear, during stop mode with osceninstop low, or during reset. 1 = 4096 eclk cycles have elapsed since ecgon was set. 0 = external clock is unstabl e, inactive, or disabled. 7.7.2 icg multiplier register n6:n0 ? icg multiplier factor bits these read/write bits change the multiplier used by the internal clock generator. the internal clock (iclk) will be: (307.2 khz 25 percent) * n a value of $00 in this register is interpreted the same as a value of $01. this register cannot be written when the cmon bit is set. reset sets this factor to $15 (decimal 21) for default frequency of 6.45 mhz 25 percent (1.613 mhz 25 percent bus). address: $0037 bit 7654321bit 0 read: n6 n5 n4 n3 n2 n1 n0 write: reset:00010101 = unimplemented figure 7-13. icg multiplier register (icgmr)
internal clock gene rator (icg) module) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 100 freescale semiconductor 7.7.3 icg trim register trim7:trim0 ? icg trim factor bits these read/write bits change the size of the internal capacitor used by the internal clock generator. by testing the frequency of the internal clock and incrementing or decrementing this factor accordingly, the accuracy of the internal clock can be improved to 2 percent. incrementing this register by one decreases the frequency by 0.195 percent of the unadj usted value. decrementing this register by one increases the frequency by 0.195 percent. this register cannot be written when the cmon bit is set. reset sets these bits to $80, centering the range of possible adjustment. 7.7.4 icg dco divider register ddiv3:ddiv0 ? icg dco divider control bits these bits indicate the number of divide-by-twos (ddiv) that follow the digitally controlled oscillator. when icgon is set, ddiv is controlled by the digital loop filter. the range of valid values for ddiv is from $0 to $9. values of $a through $f are interpreted the same as $9. since the dco is active during reset, reset has no effect on dstg and the value may vary. 7.7.5 icg dco stage register dstg7:dstg0 ? icg dco stage control bits these bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. the total number of stages is approximately equal to $1ff, so changing dstg from $00 to $ff will approximately double the period. incrementing ds tg will increase the period (decrease the frequency) by 0.202 percent to 0.368 percent (dec rementing has the opposite effect). dstg cannot be written when icgon is set to prevent inadvert ent frequency shifting. when icgon is set, dstg is controlled by the digital loop filter. since the dco is active during reset, reset has no effect on dstg and the value may vary. address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 7-14. icg trim register (icgtr) address: $0039 bit 7654321bit 0 read: ddiv3 ddiv2 ddiv1 ddiv0 write: reset:0000 uuuu = unimplemented u = unaffected figure 7-15. icg dco divider control register (icgdvr) address: $003a bit 7654321bit 0 read: dstg7 dstg6 dstg5 dstg4 dstg3 dstg2 dstg1 dstg0 write:rrrrrrrr reset: unaffected by reset r= reserved figure 7-16. icg dco stage control register (icgdsr)
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 101 chapter 8 external interrupt (irq) 8.1 introduction the irq (external interrupt) module provides a maskable interrupt input. 8.2 features features of the irq module include: ? a dedicated external interrupt pin (irq ) ? irq interrupt control bits ? hysteresis buffer ? programmable edge-only or edge and level interrupt sensitivity ? automatic interrupt acknowledge ? internal pullup resistor 8.3 functional description a logic 0 applied to the external interrupt pin can latch a central processor unit (cpu) interrupt request. figure 8-2 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: ? vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. ? software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (intscr). writing a 1 to the ack bit clears the irq latch. ? reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of these events occur: ? vector fetch or software clear ? return of the interrupt pin to logic 1
external interrupt (irq) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 102 freescale semiconductor figure 8-1. block diagram highlighting irq block and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
irq pin mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 103 figure 8-2. irq module block diagram the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the intscr mask all exte rnal interrupt requests. a latched interrupt request is not presented to the interrupt priori ty logic unless the imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. 8.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive a nd low-level-sensitive. with mode set, both of the following actions must occur to clear irq: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (intscr). t he ack bit is useful in applications that poll the addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 104. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq i/o register summary imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device ack irq synchronizer
external interrupt (irq) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 104 freescale semiconductor irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spur ious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit another interrupt request. if the ir q mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. ? return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it usef ul in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 8.5 irq module during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. see chapter 19 development support . to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect cpu interrupt flags during the break state, wr ite a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq interrupt flags. 8.6 irq status and control register the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr: ? shows the state of the irq flag ? clears the irq latch ? masks irq interrupt request ? controls triggering sensitivity of the irq interrupt pin address: $001d bit 7654321bit 0 read: irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 8-4. irq status and control register (intscr)
irq status and control register mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 105 irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only
external interrupt (irq) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 106 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 107 chapter 9 keyboard interrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0?pta7. when a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin. 9.2 features features include: ? eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask ? hysteresis buffers ? programmable edge-only or edge- and level- interrupt sensitivity ? exit from low-power modes ? i/o (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) 9.3 functional description writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. ? if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. ? if the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
keyboard interrupt module (kbi) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 108 freescale semiconductor figure 9-1. block diagram highlighting kbi block and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 109 figure 9-2. keyboard module block diagram if the modek bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: ? vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control register (intkbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. ? return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. addr.register name bit 7654321bit 0 $001a keyboard status and control register (intkbscr) see page 111. read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 112. read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-3. i/o register summary kb0ie kb7ie . . . keyboard interrupt dq ck clr v dd modek imaskk request vector fetch decoder ackk internal bus reset to pullup enable kbd7 kbd0 to pullup enable synchronizer keyf
keyboard interrupt module (kbi) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 110 freescale semiconductor the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. 9.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time fo r the internal pullup to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 9.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 9.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode.
keyboard module during break interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 111 9.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.6 keyboard module during break interrupts the system integration module (sim) controls whet her the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in t he keyboard status and control register during the break state has no effect. see 9.7.1 keyboard status and control register . 9.7 i/o registers these registers control and monitor operation of the keyboard module: ? keyboard status and control register (intkbscr) ? keyboard interrupt enable register (intkbier) 9.7.1 keyboard status and contro l register the keyboard status and control register: ? flags keyboard interrupt requests ? acknowledges keyboard interrupt requests ? masks keyboard interrupt requests ? controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (intkbscr)
keyboard interrupt module (kbi) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 112 freescale semiconductor ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 9.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin . kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin address: $001b bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 9-5. keyboard interrupt enable register (intkbier)
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 113 chapter 10 low-voltage inhibit (lvi) 10.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 10.2 features features of the lvi module include: ? programmable lvi reset ? selectable lvi trip voltage ? programmable stop mode operation 10.3 functional description figure 10-1 shows the structure of the lvi module. the lvi is enabled out of reset. the lvi module contains a bandgap reference circuit and comparator . clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. se tting the lvi 5-v or 3-v trip point bit, lvi5or3, enables the trip point voltage, v tripf , to be configured for 5-v operation. clearing the lvi5or3 bit enables the trip point voltage, v tripf , to be configured for 3-v operation. the actual trip points are shown in chapter 20 electrical specifications . note after a power-on reset (por) the lvi?s default mode of operation is 3 v. if a 5-v system is used, the user must set the lvi5or3 bit to raise the trip point to 5-v operation. note that this must be done after every power-on reset since the default will revert back to 3-v mode after each power-on reset. if the v dd supply is below the 5-v mode trip voltage but above the 3-v mode trip voltage when por is re leased, the part will operate because v tripf defaults to 3-v mode after a por. so, in a 5-v system care must be taken to ensure that v dd is above the 5-v mode trip voltage after por is released. if the user requires 5-v mode and sets the lvi5or3 bit after a power-on reset while the v dd supply is not above the v tripr for 5-v mode, the microcontroller unit (mcu) will immediatel y go into reset. the lvi in this case will hold the part in reset until either v dd goes above the rising 5-v trip point, v tripr , which will release reset or v dd decreases to approximately 0 v which will re-trigger the power-on reset and reset the trip point to 3-v operation.
low-voltage inhibit (lvi) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 114 freescale semiconductor lvistop, lvipwrd, lvi5or3, and lvirstd are in the configuration register (config1). see figure 4-2. configuration register 1 (config1) for details of the lvi?s configuration bits. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see 15.3.2.5 low-voltage inhibit (lvi) reset for details of the interaction between the sim and the lvi. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 10-1. lvi module block diagram 10.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvip wrd bit must be at 0 to enable the lvi module, and the lvirstd bit must be at 1 to disable lvi resets. 10.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be at 0 to enable the lvi module and to enable lvi resets. 10.3.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is addr.register name bit 7654321bit 0 $fe0c lvi status register (lvisr) see page 115. read:lviout0000000 write: reset:00000000 = unimplemented figure 10-2. lvi i/o register summary low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvi trip = 0 v dd lvi trip = 1 from config from config1 v dd from config1 lvirstd lvi5or3 from config1
lvi status register mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 115 continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . 10.3.4 lvi trip selection the lvi5or3 bit in the configuration register selects whether the lvi is configured for 5-v or 3-v protection. note the microcontroller is guaranteed to operate at a minimum supply voltage. the trip point (v tripf [5 v] or v tripf [3 v]) may be lower than this. (see chapter 20 electrical specifications for the actual trip point voltages.) 10.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage (see table 10-1 ). reset clears the lviout bit. 10.5 lvi interrupts the lvi module does not generate interrupt requests. 10.6 low-power modes the stop and wait instructions put the mcu in low power-consumption standby modes. 10.6.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. address: $fe0c bit 7654321bit 0 read:lviout0000000 write: reset:00000000 = unimplemented figure 10-3. lvi status register (lvisr) table 10-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < v tripf 1 v tripf < v dd < v tripr previous value
low-voltage inhibit (lvi) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 116 freescale semiconductor 10.6.2 stop mode if enabled in stop mode (lvistop set), the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode.
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 117 chapter 11 low-power modes (modes) 11.1 introduction the microcontroller (mcu) may enter two low-pow er modes: wait mode and stop mode. they are common to all hc08 mcus and are entered through in struction execution. this section describes how each module acts in the low-power modes. 11.1.1 wait mode the wait instruction puts the mcu in a low-power standby mode in which the central processor unit (cpu) clock is disabled but the bus clock continues to run. power consumption can be further reduced by disabling the lvi module and/or the timebase mo dule through bits in the config1 register. (see chapter 4 configuration register (config) .) 11.1.2 stop mode stop mode is entered when a stop instruction is ex ecuted. the cpu clock is disabled and the bus clock is disabled if the osceninstop bit in the config2 register is at a 0. (see chapter 4 configuration register (config) .) 11.2 analog-to-digi tal converter (adc) 11.2.1 wait mode the analog-to-digital converter (adc) continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch4?adch0 bits in the adc status and control register before executing the wait instruction. 11.2.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. 11.3 break module (brk) 11.3.1 wait mode if enabled, the break (brk) module is ac tive in wait mode. in the break routine, the user can subtract one from the return address on the stack if the sbsw bit in the break status register is set.
low-power mo des (modes) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 118 freescale semiconductor 11.3.2 stop mode the break module is inactive in stop mode. a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. the stop instru ction does not affect break module register states. 11.4 central processor unit (cpu) 11.4.1 wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. ? disables the cpu clock 11.4.2 stop mode the stop instruction: ? clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 11.5 internal clock generator module (icg) 11.5.1 wait mode the internal clock generator (icg) module remains acti ve in wait mode. if enabled, the icg interrupt to the cpu can bring the mcu out of wait mode. in some applications, low power-consumption is desired in wait mode and a high-frequency clock is not needed. in these applications, reduce power consumpti on by either selecting a low-frequency external clock and turn the internal clock generator off or reduce the bus frequency by minimizing the icg multiplier factor (n) before executing the wait instruction. 11.5.2 stop mode the value of the oscillator enable in stop (oscenin stop) bit in the config2 register determines the behavior of the icg in stop mode. if osceninsto p is low, the icg is disabled in stop and, upon execution of the stop instruction, all icg activi ty will cease and the ou tput clocks (cgmxclk, cgmout, copclk, and tbmclk) w ill be held low. power consumption will be minimal. if osceninstop is high, the icg is enabled in stop and activity will continue. this is useful if the timebase module (tbm) is required to bring the mcu out of stop mode. icg interrupts will not bring the mcu out of stop mode in this case. during stop mode, if osceninstop is low, several fu nctions in the icg are affected. the stable bits (ecgs and icgs) are cleared, which will enable the external clock stabilization divider upon recovery. the clock monitor is disabled (cmon = 0) which will also clear the clock monitor interrupt enable (cmie) and clock monitor flag (cmf) bits. the cs, icgon , ecgon, n, trim, ddiv, and dstg bits are unaffected.
computer operating properly module (cop) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 119 11.6 computer operatin g properly module (cop) 11.6.1 wait mode the computer operating properly (cop) module remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 11.6.2 stop mode stop mode turns off the copclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the config1 register enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 11.7 external inte rrupt module (irq) 11.7.1 wait mode the external interrupt (irq) module remains active in wait mode. clearing the imask1 bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of wait mode. 11.7.2 stop mode the irq module remains active in stop mode. clearing the imask1 bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of stop mode. 11.8 keyboard inte rrupt module (kbi) 11.8.1 wait mode the keyboard interrupt (kbi) module remains active in wait mode . clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 11.8.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 11.9 low-voltage inhibit module (lvi) 11.9.1 wait mode if enabled, the low-voltage inhibit (lvi) module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode.
low-power mo des (modes) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 120 freescale semiconductor 11.9.2 stop mode if enabled, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. 11.10 enhanced serial communic ations interface module (sci) 11.10.1 wait mode the enhanced serial communications interface (esci), or sci module for short, module remains active in wait mode. any enabled cpu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. 11.10.2 stop mode the sci module is inactive in stop mode. the stop in struction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. 11.11 serial peripheral interface module (spi) 11.11.1 wait mode the serial peripheral interface (spi) module remains active in wait mode. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. 11.11.2 stop mode the spi module is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 11.12 timer interface module (tim1 and tim2) 11.12.1 wait mode the timer interface modules (tim) remain active in wait mode. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction.
timebase module (tbm) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 121 11.12.2 stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.13 timebase module (tbm) 11.13.1 wait mode the timebase module (tbm) remains active after execut ion of the wait instruction. in wait mode, the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 11.13.2 stop mode the timebase module may remain active after execution of the stop instruction if the oscillator has been enabled to operate during stop mode through the osceninstop bit in the config2 register. the timebase module can be used in this mode to generate a periodic wakeup from stop mode. if the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode, the timebase r egister is not accessible by the cpu. if the timebase functions are not required during st op mode, reduce the power consumption by stopping the timebase before enabling the stop instruction. 11.14 exiting wait mode these events restart the cpu clock and load the program counter with the reset vector or with an interrupt vector: ? external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt ? a high-to-low trans ition on an external interrupt pin (irq pin) loads the program counter with the contents of locations: $fffa and $fffb; irq pin. ? break interrupt ? a break interrupt loads the program counter with the contents of $fffc and $fffd. ? computer operating properly module (cop) reset ? a timeout of the cop counter resets the mcu and loads the program counter with the contents of $fffe and $ffff. ? low-voltage inhibit module (lvi) reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? internal clock generator module (i cg) interrupt ? a cpu interrupt request from the icg loads the program counter with the contents of $fff8 and $fff9. ? keyboard module (kbi) interrupt ? a cpu inte rrupt request from the kbi module loads the program counter with the contents of $ffe0 and $ffe1. ? timer 1 interface module (tim1) interrupt ? a cpu interrupt request from the tim1 loads the program counter with the contents of: ? $fff2 and $fff3; tim1 overflow ? $fff4 and $fff5; tim1 channel 1 ? $fff6 and $fff7; tim1 channel 0
low-power mo des (modes) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 122 freescale semiconductor ? timer 2 interface module (tim2) interrupt ? a cpu interrupt request from the tim2 loads the program counter with the contents of: ? $ffec and $ffed; tim2 overflow ? $ffee and $ffef; tim2 channel 1 ? $fff0 and $fff1; tim2 channel 0 ? serial peripheral interface module (spi) interrupt ? a cpu interrupt request from the spi loads the program counter with the contents of: ? $ffe8 and $ffe9; spi transmitter ? $ffea and $ffeb; spi receiver ? serial communications interface module (sci) interrupt ? a cpu interrupt request from the sci loads the program counter with the contents of: ? $ffe2 and $ffe3; sci transmitter ? $ffe4 and $ffe5; sci receiver ? $ffe6 and $ffe7; sci receiver error ? analog-to-digital converter module (adc) interrupt ? a cpu interrupt request from the adc loads the program counter with the contents of: $ffde and $ffdf; adc conversion complete. ? timebase module (tbm) interrupt ? a cpu interru pt request from the tbm loads the program counter with the contents of: $ffdc and $ffdd; tbm interrupt. 11.15 exiting stop mode these events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: ? external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt ? a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: ? $fffa and $fffb; irq pin ? $ffe0 and $ffe1; keyboard interrupt pins ? low-voltage inhibit (lvi) reset ? a power supply voltage below the lvi tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? break interrupt ? a break interrupt loads the program counter with the contents of locations $fffc and $fffd. ? timebase module (tbm) interrupt ? a tbm interrupt loads the program counter with the contents of locations $ffdc and $ffdd when the timebase counter has rolled over. this allows the tbm to generate a periodic wakeup from stop mode. upon exit from stop mode, the system clocks begin running after an o scillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks fo r 4096 cgmxclk cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the config1 register controls the oscillator stabilization delay during stop recovery. setting ssrec reduces stop recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. note use the full stop recovery time (ssrec = 0) in applications that use an external crystal.
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 123 chapter 12 input/output (i/o) ports (ports) 12.1 introduction bidirectional input-output (i/o) pins form five parall el ports. all i/o pins are programmable as inputs or outputs. all individual bits within port a, port c, and port d are software configurable with pullup devices if configured as input port bits. the pullup devices are automatically and dynam ically disabled when a port bit is switched to output mode. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 126. read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 128. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 130. read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) see page 132. read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) see page 126. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 128. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 12-1. i/o port register summary
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 124 freescale semiconductor $0006 data direction register c (ddrc) see page 130. read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) see page 133. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) see page 135. read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $000c data direction register e (ddre) see page 136. read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d port a input pullup enable register (ptapue) see page 127. read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 131. read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f port d input pullup enable register (ptdpue) see page 134. read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented figure 12-1. i/o port register summary (continued)
introduction mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 125 table 12-1. port control register bits summary port bit ddr module control pin a 0 ddra0 kbd kbie0 pta0/kbd0 1 ddra1 kbie1 pta1/kbd1 2 ddra2 kbie2 pta2/kbd2 3 ddra3 kbie3 pta3/kbd3 4 ddra4 kbie4 pta4/kbd4 5 ddra5 kbie5 pta5/kbd5 6 ddra6 kbie6 pta6/kbd6 7 ddra7 kbie7 pta7/kbd7 b 0 ddrb0 adc adch4?adch0 ptb0/ad0 1 ddrb1 ptb1/ad1 2 ddrb2 ptb2/ad2 3 ddrb3 ptb3/ad3 4 ddrb4 ptb4/ad4 5 ddrb5 ptb5/ad5 6 ddrb6 ptb6/ad6 7 ddrb7 ptb7/ad7 c 0 ddrc0 ptc0 1 ddrc1 ptc1 2 ddrc2 ptc2 3 ddrc3 ptc3 4 ddrc4 ptc4 5 ddrc5 ptc5 6 ddrc6 ptc6 d 0 ddrd0 spi spe ptd0/ss 1 ddrd1 ptd1/miso 2 ddrd2 ptd2/mosi 3 ddrd3 ptd3/spsck 4 ddrd4 tim1 els0b:els0a ptd4/t1ch0 5 ddrd5 els1b:el s1a ptd5/t1ch1 6 ddrd6 tim2 els0b:els0a ptd6/t2ch0 7 ddrd7 els1b:el s1a ptd7/t2ch1 e 0 ddre0 sci ensci pte0/txd 1 ddre1 pte1/rxd 2 ddre2 pte2 3 ddre3 icg ecgon: extxtalen pte3/osc2 4 ddre4 ecgon pte4/osc1
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 126 freescale semiconductor 12.2 port a port a is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (kbi) module. port a also has software configurable pullup devices if configured as an input port. 12.2.1 port a data register the port a data register (pta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd7?kbd0 ? keyboard inputs the keyboard interrupt enable bits, kbie7?kbie0, in the keyboard interrupt control register (kbicr) enable the port a pins as external interrupt pins. see chapter 9 keyboard interrupt module (kbi). 12.2.2 data dir ection register a data direction register a (ddra) determines whether eac h port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the co rresponding port a pin; a 0 disables the output buffer. ddra7?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra7?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kbd7 kbd6 kbd5 kbd4 kbd3 kbd2 kbd1 kbd0 figure 12-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 12-3. data direction register a (ddra)
port a mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 127 figure 12-4 shows the port a i/o logic. figure 12-4. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port a pins. 12.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) contains a software configur able pullup device for each of the eight port a pins. each bit is individually conf igurable and requires that the data direction register, ddra, bit be configured as an input. ea ch pullup is automati cally and dynamically disabled when a port bit?s ddra is configured for output mode . table 12-2. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device ddra7?ddra0 pin pta7?pta0 (3) 3. writing affects data register, but does not affect input. 0 0 x input, hi-z (4) 4. hi-z = high impedance ddra7?ddra0 pin pta7?pta0 (3) x 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 address: $0004 bit 7654321bit 0 read: ptapue7 ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 12-5. port a input pullup enable register (ptapue) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus v dd ptapuex 45 k
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 128 freescale semiconductor ptapue7?ptapue0 ? port a input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port a pin configured to have internal pullup 0 = corresponding port a pin has internal pullup disconnected 12.3 port b port b is an 8-bit special-function port that shares al l eight of its pins with the analog-to-digital converter (adc) module. 12.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. ad7?ad0 ? analog-to-digital input bits ad7?ad0 are pins used for the input channels to the analog-to-digital converter module. the channel select bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. note care must be taken when reading port b while applying analog voltages to ad7?ad0 pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/adx pin, while ptb is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. 12.3.2 data dir ection register b data direction register b (ddrb) determines whether eac h port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the co rresponding port b pin; a 0 disables the output buffer. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: ad 7ad6ad5ad4ad3ad2ad1ad0 figure 12-6. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-7. data direction register b (ddrb)
port c mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 129 ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data directio n. reset clears ddrb7?ddrb0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 12-8 shows the port b i/o logic. figure 12-8. port b i/o circuit when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port b pins. 12.4 port c port c is a 7-bit, general-purpose bidirectional i/o port. port c also has software configurable pullup devices if configured as an input port. table 12-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 130 freescale semiconductor 12.4.1 port c data register the port c data register (ptc) contains a dat a latch for each of the seven port c pins. note bit 6 and bit 5 of ptc are not available in the 42-pin shrink dual in-line package. ptc6?ptc0 ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 12.4.2 data dir ection register c data direction register c (ddrc) determines whether eac h port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a 0 disables the output buffer. ddrc6?ddrc0 ? data direction register c bits these read/write bits control por t c data direction. reset clears ddrc6?ddrc0, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 12-11 shows the port c i/o logic. note for those devices packaged in a 42-pin shrink dual in-line package, ptc5 and ptc6 are connected to ground internally. ddrc5 and ddrc6 should be set to a 0 to configure ptc5 and ptc6 as inputs. address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset = unimplemented figure 12-9. port c data register (ptc) address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 12-10. data direction register c (ddrc)
port c mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 131 figure 12-11. port c i/o circuit when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port c pins. 12.4.3 port c input pullup enable register the port c input pullup enable register (ptcpue) contains a software configur able pullup device for each of the seven port c pins. each bit is individually configurable and requires that the data direction register, ddrc, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrc is configured for output mode. table 12-4. port c pin functions ptcpue bit ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 10x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device. ddrc6?ddrc0 pin ptc6?ptc0 (3) 3. writing affects data register, but does not affect input. 0 0 x input, hi-z (4) 4. hi-z = high impedance ddrc6?ddrc0 pin ptc6?ptc0 (3) x 1 x output ddrc6?ddrc0 ptc6?ptc0 ptc6?ptc0 address: $000e bit 7654321bit 0 read: 0 ptcpue6 ptcpue5 ptcpue4 ptcpue3 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 = unimplemented figure 12-12. port c input pullup enable register (ptcpue) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus v dd ptcpuex 45 k
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 132 freescale semiconductor ptcpue6?ptcpue0 ? port c input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port c pin configured to have internal pullup 0 = corresponding port c pin internal pullup disconnected 12.5 port d port d is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (spi) module and four of its pins with two timer interface (tim1 and tim2) modules. port d also has software configurable pullup devices if configured as an input port. 12.5.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd7?ptd0 ? port d data bits these read/write bits are software-programmable. da ta direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. t2ch1 and t2ch0 ? timer 2 channel i/o bits the ptd7/t2ch1?ptd6/t2ch0 pins are the tim2 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, dete rmine whether the ptd7/t2ch1?ptd 6/t2ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface module (tim) . t1ch1 and t1ch0 ? timer 1 channel i/o bits the ptd7/t1ch1?ptd6/t1ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb and elsxa, determine whether the ptd7/t1ch1?ptd6/t1ch0 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 18 timer interface module (tim) . spsck ? spi serial clock the ptd3/spsck pin is the serial clock input of the spi module. when the spe bit is clear, the ptd3/spsck pin is available for general-purpose i/o. mosi ? master out/slave in the ptd2/mosi pin is the master out/slave in term inal of the spi module. when the spe bit is clear, the ptd2/mosi pin is available for general-purpose i/o. miso ? master in/slave out the ptd1/miso pin is the master in/slave out term inal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the ptd0/ss pin is available for general-purpose i/o. address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: t2ch1 t2ch0 t1ch1 t1ch0 spsck mosi miso ss figure 12-13. port d data register (ptd)
port d mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 133 data direction register d (ddrd) does not affect th e data direction of port d pins that are being used by the spi module. however, the ddrd bits alwa ys determine whether reading port d returns the states of the latches or the states of the pins. see table 12-5. ss ? slave select the ptd0/ss pin is the slave select input of the sp i module. when the spe bit is clear, or when the spi master bit, spmstr, is set, the ptd0/ss pin is available for general-purpose i/o. when the spi is enabled, the ddrb0 bit in da ta direction register b (ddrb ) has no effect on the ptd0/ss pin. 12.5.2 data dir ection register d data direction register d (ddrd) determines whether ea ch port d pin is an input or an output. writing a 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a 0 disables the output buffer. ddrd7?ddrd0 ? data direction register d bits these read/write bits control por t d data direction. reset clears ddrd7?ddrd0, configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. figure 12-15 shows the port d i/o logic. figure 12-15. port d i/o circuit address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 12-14. data direction register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus v dd ptdpuex 30 k
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 134 freescale semiconductor when bit ddrdx is a 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-5 summarizes the operation of the port d pins. 12.5.3 port d input pullup enable register the port d input pullup enable register (ptdpue) contains a software configur able pullup device for each of the eight port d pins. each bit is individually configurable and require s that the data direction register, ddrd, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrd is configured for output mode. ptdpue7?ptdpue0 ? port d input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port d pin configured to have internal pullup 0 = corresponding port d pin ha s internal pullup disconnected 12.6 port e port e is a 5-bit special-function por t that shares two of its pins with the serial communications interface (sci) module and two of its pins with the internal clock generator (icg). table 12-5. port d pin functions ptdpue bit ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 10x (1) 1. x = don?t care input, v dd (2) 2. i/o pin pulled up to v dd by internal pullup device. ddrd7?ddrd0 pin ptd7?ptd0 (3) 3. writing affects data register, but does not affect input. 0 0 x input, hi-z (4) 4. hi-z = high imp[edance ddrd7?ddrd0 pin ptd7?ptd0 (3) x 1 x output ddrd7?ddrd0 ptd7?ptd0 ptd7?ptd0 address: $000f bit 7654321bit 0 read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 figure 12-16. port d input pullup enable register (ptdpue)
port e mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 135 12.6.1 port e data register the port e data register contains a data latch for each of the five port e pins. pte4-pte0 ? port e data bits these read/write bits are software-programmable. data direction of each port e pin is under the control of the corresponding bit in data direction regi ster e. reset has no effect on port edata. note data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. see table 12-6 . osc2 and osc1 ? osc2 and osc1 bits under software control, pte4 and pte3 can be configured as external clock inputs and outputs. pte3 will become an output clock, osc2, if selected in the configuration registers and enabled in the icg registers. pte4 will become an external input clock source, osc1, if selected in the configuration registers and enabled in the icg registers. see chapter 7 internal clock generator (icg) module) and chapter 5 computer operat ing properly (cop) module . while configured as oscillator pins, writes have no effect and reads return undefined values. rxd ? sci receive data input the pte1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is available for general-purpose i/o. see chapter 14 enhanced serial communi cations interface (esci) module . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte0/txd pin is available for general-purpose i/o. see chapter 14 enhanced serial communi cations interface (esci) module . 12.6.2 data dir ection register e data direction register e (ddre) determines whether eac h port e pin is an input or an output. writing a 1 to a ddre bit enables the output buffer for the co rresponding port e pin; a 0 disables the output buffer. address: $0008 bit 7654321bit 0 read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: osc1 osc2 rxd txd = unimplemented figure 12-17. port e data register (pte)
input/output (i/o) ports (ports) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 136 freescale semiconductor ddre4?ddre0 ? data direction register e bits these read/write bits control port e data directio n. reset clears ddre4?ddre0, configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction regist er e bits from 0 to 1. figure 12-19 shows the port e i/o logic. figure 12-19. port e i/o circuit when bit ddrex is a 1, reading address $0008 reads the ptex data latch. when bit ddrex is a 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-6 summarizes the operation of the port e pins. address: $000c bit 7654321bit 0 read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented figure 12-18. data direction register e (ddre) table 12-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddre4?ddre0 pin pte4?pte0 (3) 3. writing affects data register, but does not affect input. 1 x output ddre4?ddre0 pte4?pte0 pte4?pte0 read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 137 chapter 13 resets and interrupts 13.1 introduction resets and interrupts are responses to exceptional event s during program execution. a reset re-initializes the mcu to its startup condition. an interrupt vectors the program counter to a service routine. 13.2 resets a reset immediately returns the mcu to a known star tup condition and begins program execution from a user-defined memory location. 13.2.1 effects a reset: ? immediately stops the operation of the instruction being executed ? initializes certain control and status bits ? loads the program counter with a user-defined reset vector address from locations $fffe and $ffff ? selects cgmxclk divided by four as the bus clock 13.2.2 external reset a logic 0 applied to the rst pin for a time, t irl , generates an external reset. an external reset sets the pin bit in the sim reset status register. 13.2.3 internal reset sources: ? power-on reset (por) ? computer operating properly (cop) ? low-power reset circuits ? illegal opcode ? illegal address all internal reset sources pull the rst pin low for 32 cgmxclk cycles to allow resetting of external devices. the mcu is held in reset for an additi onal 32 cgmxclk cycles after releasing the rst pin. see figure 13-1 .
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 138 freescale semiconductor figure 13-1. internal reset timing 13.2.3.1 power-on reset (por) a power-on reset (por) is an internal reset caused by a positive transition on the v dd pin. v dd at the por must go completely to 0 v to reset the mcu. this distinguishes between a reset and a por. the por is not a brown-out detector, low-voltage detector, or glitch detector. a power-on reset: ? holds the clocks to the cpu and modules inactive for an oscill ator stabilization delay of 4096 cgmxclk cycles ? drives the rst pin low during the oscillator stabilization delay ? releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay ? releases the cpu to begin the reset vector se quence 64 cgmxclk cycles after the oscillator stabilization delay ? sets the por bit in the sim reset status regi ster and clears all other bits in the register figure 13-2. power-on reset recovery 13.2.3.2 computer operating properly (cop) reset a cop reset is an internal reset caused by an over flow of the cop counter. a cop reset sets the cop bit in the system integration m odule (sim) reset status register. to clear the cop counter and prevent a cop reset, write any value to the cop control register at location $ffff. rst pin pulled low by mcu internal 32 cycles 32 cycles cgmxclk reset porrst (1) osc1 cgmxclk cgmout rst pin internal 4096 cycles 32 cycles 32 cycles 1. porrst is an internally generated power-on reset pulse. reset
resets mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 139 13.2.3.3 low-voltage inhibit reset a low-voltage inhibit (lvi) reset is an internal reset caused by a drop in the power supply voltage to the lvi tripf voltage. an lvi reset: ? holds the clocks to the cpu and modules inactive for an oscill ator stabilization delay of 4096 cgmxclk cycles after the power supply voltage rises to the lvi tripr voltage ? drives the rst pin low for as long as v dd is below the lvi tripr voltage and during the oscillator stabilization delay ? releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay ? releases the cpu to begin the reset vector se quence 64 cgmxclk cycles after the oscillator stabilization delay ? sets the lvi bit in the sim reset status register 13.2.3.4 illegal opcode reset an illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. an illegal opcode reset sets the ilop bit in the sim reset status register. if the stop enable bit, stop, in the config1 register is a 0, the stop instruction causes an illegal opcode reset. 13.2.3.5 illegal address reset an illegal address reset is an internal reset caused by opcode fetch from an unmapped address. an illegal address reset sets the ilad bit in the sim reset status register. a data fetch from an unmapped address does not generate a reset. 13.2.4 sim reset status register this read-only register contains flags to show rese t sources. all flag bits are automatically cleared following a read of the register. reset service can read the sim reset status register to clear the register after power-on reset and to determine the source of any subsequent reset. the register is initialized on power-up as shown with the por bit set and all other bits cleared. during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 cgmxclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the srsr may be set in addition to whatever other bits are set. note only a read of the sim reset status register clears all reset flags. after multiple resets from different sources without reading the register, multiple flags remain set.
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 140 freescale semiconductor por ? power-on reset flag 1 = power-on reset since last read of srsr 0 = read of srsr since last power-on reset pin ? external reset flag 1 = external reset via rst pin since last read of srsr 0 = por or read of srsr since last external reset cop ? computer operating properly reset bit 1 = last reset caused by timeout of cop counter 0 = por or read of srsr since any reset ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr since any reset ilad ? illegal address reset bit 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr since any reset modrst ? monitor mode entry module reset bit 1 = last reset caused by forced monitor mode entry. 0 = por or read of srsr since any reset lvi ? low-voltage inhibit reset bit 1 = last reset caused by low-power supply voltage 0 = por or read of srsr since any reset 13.3 interrupts an interrupt temporarily changes the sequence of progr am execution to respond to a particular event. an interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation. 13.3.1 effects an interrupt: ? saves the cpu registers on the stack. at the end of the interrupt, the rti instruction recovers the cpu registers from the stack so that normal processing can resume. ? sets the interrupt mask (i bit) to prevent additional interrupts. once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. ? loads the program counter with a user-defined vector address address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 13-3. sim reset status register (srsr)
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 141 figure 13-4. interrupt stacking order after every instruction, the cpu checks all pending interrupts if the i bit is not set. if more than one interrupt is pending when an instruction is done, the hi ghest priority interrupt is serviced first. in the example shown in figure 13-5 , if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 13-5 . interrupt recognition example condition code register accumulator index register (low byte) (1) program counter (high byte) program counter (low byte) ? ? ? ? ? ? 1 2 3 4 5 5 4 3 2 1 stacking order 1. high byte of index register is not stacked. $00ff default address on reset unstacking order cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 142 freescale semiconductor figure 13-6. interrupt processing the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine no no no yes no no yes no yes yes from reset break i bit set? irq interrupt icg interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? interrupt yes other interrupts no swi instruction rti instruction ? ? ? ? ? ?
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 143 modifies the h register or uses th e indexed addressing mode, save the h register and then restore it prior to exiting the routine. 13.3.2 sources the sources in table 13-1 can generate cpu interrupt requests. 13.3.2.1 software interrupt (swi) instruction the software interrupt instruction (swi) causes a non-maskable interrupt. note a software interrupt pushes pc onto the stack. an swi does not push pc ? 1, as a hardware interrupt does. table 13-1. interrupt sources source flag mask (1) 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. int register flag priority (2) 2. 0 = highest priority vector address reset none none none 0 $fffe ? $ffff swi instruction n one none none 0 $fffc ? $fffd irq pin irqf imask1 if1 1 $fffa ? $fffb icg clock monitor cmf cmie if2 2 $fff8?$fff9 tim1 channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim1 channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim1 overflow tof toie if5 5 $fff2?$fff3 tim2 channel 0 ch0f ch0ie if6 6 $fff0?$fff1 tim2 channel 1 ch1f ch1ie if7 7 $ffee?$ffef tim2 overflow tof toie if8 8 $ffec?$ffed spi receiver full sprf sprie if9 9 $ffea?$ffeb spi overflow ovrf errie spi mode fault modf errie spi transmitter empty spte sptie if10 10 $ffe8?$ffe9 sci receiver overrun or orie if11 11 $ffe6?$ffe7 sci noise fag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4?$ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2?$ffe3 sci transmission complete tc tcie keyboard pin keyf imaskk if14 14 $ffe0?$ffe1 adc conversion complete coco aien if15 15 $ffde?$ffdf timebase tbif tbie if16 16 $ffdc?$ffdd
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 144 freescale semiconductor 13.3.2.2 break interrupt the break module causes the cpu to execute an swi instruction at a software-programmable break point. 13.3.2.3 irq pin a logic 0 on the irq1 pin latches an external interrupt request. 13.3.2.4 internal clock generator (icg) the icg can generate a cpu interrupt request every time the selected internal or external clock becomes inactive. when the clock monitor cmon bit is set and the currently selected clock becomes inactive, the clock monitor interrupt flag cmf is set. the clock mo nitor interrupt enable bit (cmie) enables icg cpu interrupt requests. cmie, cmf, and cmon are in the icgcr control register. 13.3.2.5 timer interface module 1 (tim1) tim1 cpu interrupt sources: ? tim1 overflow flag (tof) ? the tof bit is set when the tim1 counter value rolls over to $0000 after matching the value in the tim1 counter modulo registers. the tim1 overflow interrupt enable bit, toie, enables tim1 overflow cpu interrupt r equests. tof and toie are in the tim1 status and control register. ? tim1 channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim1 cpu interrupt requests. chxf and chxie are in the tim1 channel x status and control register. 13.3.2.6 timer interface module 2 (tim2) tim2 cpu interrupt sources: ? tim2 overflow flag (tof) ? the tof bit is set when the tim2 counter value rolls over to $0000 after matching the value in the tim2 counter modulo registers. the tim2 overflow interrupt enable bit, toie, enables tim2 overflow cpu interrupt r equests. tof and toie are in the tim2 status and control register. ? tim2 channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim2 cpu interrupt requests. chxf and chxie are in the tim2 channel x status and control register. 13.3.2.7 serial peripheral interface (spi) spi cpu interrupt sources: ? spi receiver full bit (sprf) ? the sprf bit is set every time a byte transfers from the shift register to the receive data register. the spi receiver interrupt enable bit, sprie, enables sprf cpu interrupt requests. sprf is in the spi status and control register and sprie is in the spi control register. ? spi transmitter empty (spte) ? the spte bit is set every time a byte transfers from the transmit data register to the shift register. the spi transmit interrupt enable bit, sptie, enables spte cpu interrupt requests. spte is in the spi status and control register and sptie is in the spi control register.
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 145 ? mode fault bit (modf) ? the modf bit is set in a slave spi if the ss pin goes high during a transmission with the mode fault enable bit (modfen) set. in a master spi, the modf bit is set if the ss pin goes low at any time with the modfen bit set. the error interrupt enable bit, errie, enables modf cpu interrupt requests. modf, modfen, and errie are in the spi status and control register. ? overflow bit (ovrf) ? the ovrf bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. the error interrupt enable bit, errie, enables ovrf cpu interrupt requests. ovrf and errie are in the spi status and control register. 13.3.2.8 serial communications interface (sci) sci cpu interrupt sources: ? sci transmitter empty bit (scte) ? scte is set when the sci data register transfers a character to the transmit shift register. the sci transmit interrupt enable bit, sctie, enables transmitter cpu interrupt requests. scte is in sci status register 1. sctie is in sci control register 2. ? transmission complete bit (tc) ? tc is set when the transmit shift register and the sci data register are empty and no break or idle characte r has been generated. the transmission complete interrupt enable bit, tcie, enables transmitter cpu interrupt requests. tc is in sci status register 1. tcie is in sci control register 2. ? sci receiver full bit (scrf) ? scrf is set when the receive shift register transfers a character to the sci data register. the sci receive interrupt enable bit, scrie, enables receiver cpu interrupts. scrf is in sci status register 1. scrie is in sci control register 2. ? idle input bit (idle) ? idle is set when 10 or 11 consecutive 1s shift in from the rxd pin. the idle line interrupt enable bit, ilie, enables idle cpu interrupt requests. idle is in sci status register 1. ilie is in sci control register 2. ? receiver overrun bit (or) ? or is set when the re ceive shift register shifts in a new character before the previous character was read from t he sci data register. the overrun interrupt enable bit, orie, enables or to generate sci error cpu inte rrupt requests. or is in sci status register 1. orie is in sci control register 3. ? noise flag (nf) ? nf is set when the sci detec ts noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, enables nf to generate sci error cpu interrupt requests. nf is in sci status register 1. neie is in sci control register 3. ? framing error bit (fe) ? fe is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, enables fe to generate sci error cpu interrupt requests. fe is in sci status register 1. feie is in sci control register 3. ? parity error bit (pe) ? pe is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, enables pe to generate sci error cpu interrupt requests. pe is in sci status register 1. peie is in sci control register 3. 13.3.2.9 kbd0 ?kbd7 pins a logic 0 on a keyboard interrupt pin latches an external interrupt request. 13.3.2.10 analog-to-digital converter (adc) when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. the coco bit is not used as a conversion complete flag when interrupts are enabled.
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 146 freescale semiconductor 13.3.2.11 timebase module (tbm) the timebase module can interrupt the cpu on a regul ar basis with a rate defined by tbr2?tbr0. when the timebase counter chain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the counter chain overflow will generate a cpu interrupt request. interrupts must be acknowledged by writing a 1 to the tack bit. 13.3.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 13-2 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 13-2. interrupt source flags interrupt source interrupt status register flag reset ? swi instruction ? irq pin if1 icg clock monitor if2 tim1 channel 0 if3 tim1 channel 1 if4 tim1 overflow if5 tim2 channel 0 if6 tim2 channel 1 if7 tim2 overflow if8 spi receive if9 spi transmit if10 sci error if11 sci receive if12 sci transmit if13 keyboard if14 adc conversion complete if15 timebase if16
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 147 13.3.3.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present bit 1 and bit 0 ? always read 0 13.3.3.2 interrupt status register 2 if14?if7 ? interrupt flags 14?7 these flags indicate the presence of interrupt requests from the sources shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present 13.3.3.3 interrupt status register 3 if16?if15 ? interrupt flags 16?15 this flag indicates the presence of an in terrupt request from the source shown in table 13-2 . 1 = interrupt request present 0 = no interrupt request present bits 7?2 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r = reserved figure 13-7. interrupt status register 1 (int1) address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r = reserved figure 13-8. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:000000if16if15 write:rrrrrrrr reset:00000000 r = reserved figure 13-9. interrupt status register 3 (int3)
resets and interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 148 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 149 chapter 14 enhanced serial communications interface (esci) module 14.1 introduction the enhanced serial communications interface (esc i) module allows asynchronous communications with peripheral devices and other microcontroller units (mcu). 14.2 features features include: ? full-duplex operation ? standard mark/space non-retu rn-to-zero (nrz) format ? programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? separate receiver and transmitter centra l processor unit (cpu) interrupt requests ? programmable transmitter output polarity ? two receiver wakeup methods: ? idle line wakeup ? address mark wakeup ? interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection 14.3 pin name conventions the generic names of the esci input/output (i/o) pins are: ? rxd (receive data) ? txd (transmit data) esci i/o lines are implemented by s haring parallel i/o port pins. the full name of an esci input or output reflects the name of the shared port pin. table 14-1 shows the full names and the generic names of the esci i/o pins. the generic pin names appear in the text of this section.
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 150 freescale semiconductor figure 14-1. block diagram highlighting esci block and pins table 14-1. pin name conventions generic pin names rxd txd full pin names pte1/rxd pte0/txd single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 151 14.4 functional description figure 14-2 shows the structure of the esci module. t he esci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote dev ices, including other mcus. the transmitter and receiver of the esci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the esci, writes the data to be transmitted, and processes received data. for reference, a summary of the esci module input/output registers is provided in figure 14-4 . figure 14-2. esci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 orie feie peie bkf rpf esci data receive shift register esci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register transmitter interrupt control receiver interrupt control error interrupt control control ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud rate generator bus clock rxd txd pre- scaler arbiter- sci_txd rxd linr lint
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 152 freescale semiconductor 14.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 14-3 . figure 14-3. sci data formats addr. register name bit 7654321 bit 0 $0009 esci prescaler register (scpsc) see page 172. read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 $000a esci arbiter control register (sciactl) see page 176. read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 $000b esci arbiter data register (sciadat) see page 177. read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 $0013 esci control register 1 (scc1) see page 163. read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 esci control register 2 (scc2) see page 165. read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 esci control register 3 (scc3) see page 167. read: r8 t8 r r orie neie feie peie write: reset:u0000000 $0016 esci status register 1 (scs1) see page 168. read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 esci status register 2 (scs2) see page 170. read:000000bkfrpf write: reset:00000000 $0018 esci data register (scdr) see page 171. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 esci baud rate register (scbr) see page 171. read: r linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 14-4. esci i/o register summary bit 5 bit 0 bit 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit next start bit next start bit stop bit stop bit 8-bit data format (bit m in scc1 clear) 9-bit data format (bit m in scc1 set) start bit start bit
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 153 14.4.2 transmitter figure 14-5 shows the structure of the sci transm itter and the registers are summarized in figure 14-4 . figure 14-5. esci transmitter 14.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in esci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in esci control register 3 (scc3) is the ninth bit (bit 8). 14.4.2.2 character transmission during an esci transmission, the transmit shift regist er shifts a character out to the txd pin. the esci data register (scdr) is the write-only buffer between t he internal data bus and the transmit shift register. pen pty h876543210l 11-bit transmit stop start t8 scte sctie tcie sbk tc bus clock parity generation msb esci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register tc sctie tcie scte transmitter cpu interrupt request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sci_txd pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 lint
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 154 freescale semiconductor to initiate an esci transmission: 1. enable the esci by writing a 1 to the enable esci bit (ensci) in esci control register 1 (scc1). 2. enable the transmitter by writing a 1 to the trans mitter enable bit (te) in esci control register 2 (scc2). 3. clear the esci transmitter empty bit (scte) by first reading esci status register 1 (scs1) and then writing to the scdr. for 9-bit data, also write the t8 bit in scc3. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the transmit shift register with a preamble of 1s. after the preamble shifts out, control logic transfers the s cdr data into the transmit shift register. a 0 start bit automatically goes into the least significant bit (lsb) position of the transmit shift register. a 1 stop bit goes into the most significant bit (msb) position. the esci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the esci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in esci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 14.4.2.3 break characters writing a 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. for txinv = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1 and the linr bits in scbr. as long as sbk is at 1, transmitter logic conti nuously loads break charac ters into the transmit shift register. after software clears the sbk bit, the shift register finis hes transmitting the last break character and then transmits at least one 1. the automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. when linr is cleared in scbr, the esci recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive 0 data bits. when linr is set in scbr, the esci recognizes a break character when a start bit is followed by 9 or 10 0 data bits and a 0 where the stop bit shoul d be, resulting in a total of 11 or 12 consecutive 0 data bits. receiving a break character has these effects on esci registers: ? sets the framing error bit (fe) in scs1 ? sets the esci receiver full bit (scrf) in scs1 ? clears the esci data register (scdr) ? clears the r8 bit in scc3 ? sets the break flag bit (bkf) in scs2 ? may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 14.4.2.4 idle characters for txinv = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission.
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 155 if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. note when queueing an idle character, return the te bit to 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. 14.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in esci control r egister 1 (scc1) reverses the polarity of transmitted data. all transmitted values including idle, break, st art, and stop bits, are inverted when txinv is at 1. see 14.8.1 esci control register 1 . 14.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the esci transmitter: ? esci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the esci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. ? transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 14.4.3 receiver figure 14-6 shows the structure of the esci receiver. the receiver i/o registers are summarized in figure 14-4 . 14.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit dat a. the state of the m bit in esci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in esci control register 3 (scc3) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 14.4.3.2 character reception during an esci reception, the receive shift register sh ifts characters in from the rxd pin. the esci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the esci receiver full bit, scrf, in esci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the esci rece ive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request.
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 156 freescale semiconductor figure 14-6. esci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery or orie nf neie fe feie pe peie scrie scrf ilie idle wakeup logic parity checking msb error cpu cpu interrupt esci data register r8 scrie ilie rwu scrf idle internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 rxd bus clock pre- scaler pds1 pds2 pds0 pssb3 pssb4 pssb2 pssb1 pssb0 linr request interrupt request orie neie feie peie or nf fe pe
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 157 14.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at these times (see figure 14-7 ): ? after every start bit ? after the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit oc curs, the rt clock begins to count to 16. figure 14-7. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-2 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-3 summarizes the results of the data bit samples. table 14-2. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 158 freescale semiconductor note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-4 summarizes the results of the stop bit samples. 14.4.3.4 framing errors if the data recovery logic does not detect a 1 where t he stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. 14.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. table 14-3. data bit recovery rt8, rt9, and rt10 samples d ata bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-4. stop bit recovery rt8, rt9, and rt10 samples f raming error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 159 slow data tolerance figure 14-8 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 inst ead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 14-8. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles +10rtcycles=154rtcycles. with the misaligned character shown in figure 14-8 , the receiver counts 154 rt cycles at the point when the count of the transmitti ng device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is: for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles +10rtcycles=170rtcycles. with the misaligned character shown in figure 14-8 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: fast data tolerance figure 14-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 14-9. fast data msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data sample receiver rt clock
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 160 freescale semiconductor for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles +10rtcycles=154rtcycles. with the misaligned character shown in figure 14-9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of t he stop bit takes the receiver 10 bit times 16 rt cycles +10rtcycles=170rtcycles. with the misaligned character shown in figure 14-9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 14.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: 1. address mark ? an address mark is a 1 in th e msb position of a received character. when the wake bit is set, an address mark wakes the receiv er from the standby st ate by clearing the rwu bit. the address mark also sets the esci receiver full bit, scrf. software can then compare the character containing the address mark to the user -defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. 2. idle input line condition ? when the wake bit is cl ear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the esci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle will cause the receiver to wake up. 154 160 ? 154 ------------------------- - 100 3.90%. = 170 176 ? 170 ------------------------- - 100 3.53%. =
low-power modes mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 161 14.4.3.7 receiver interrupts these sources can generate cpu interrupt requests from the esci receiver: ? esci receiver full (scrf) ? the scrf bit in sc s1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the esci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. ? idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 14.4.3.8 error interrupts these receiver error flags in scs1 can generate cpu interrupt requests: ? receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate esci error cpu interrupt requests. ? noise flag (nf) ? the nf bit is set when t he esci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate esci error cpu interrupt requests. ? framing error (fe) ? the fe bit in scs1 is set when a 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate esci error cpu interrupt requests. ? parity error (pe) ? the pe bit in scs1 is set when the esci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate esci error cpu interrupt requests. 14.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 14.5.1 wait mode the esci module remains active in wait mode. any enabled cpu interrupt request from the esci module can bring the mcu out of wait mode. if esci module functions are not required during wait mode, reduce power consum ption by disabling the module before executing the wait instruction. 14.5.2 stop mode the esci module is inactive in stop mode. the stop instruction does not affect esci register states. esci module operation resumes after the mcu exits stop mode. because the internal clock is i nactive during stop mode, entering stop mode during an esci transmission or reception results in invalid data.
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 162 freescale semiconductor 14.6 esci during br eak module interrupts the bcfe bit in the break flag control register (sbfcr) enables software to clear status bits during the break state. see chapter 19 development support . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 14.7 i/o signals port e shares two of its pins with th e esci module. the two esci i/o pins are: ? pte0/txd ? transmit data ? pte1/rxd ? receive data 14.7.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the esci transmitter. the esci shares the pte0/txd pin with port e. when the esci is enabled, the pte0/txd pin is an output regardless of the state of the ddre0 bit in data direction register e (ddre). 14.7.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the es ci receiver. the esci shares the pte1/rxd pin with port e. when the esci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). 14.8 i/o registers these i/o registers control and monitor esci operation: ? esci control register 1, scc1 ? esci control register 2, scc2 ? esci control register 3, scc3 ? esci status register 1, scs1 ? esci status register 2, scs2 ? esci data register, scdr ? esci baud rate register, scbr ? esci prescaler register, scpsc ? esci arbiter control register, sciactl ? esci arbiter data register, sciadat
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 163 14.8.1 esci control register 1 esci control register 1 (scc1): ? enables loop mode operation ? enables the esci ? controls output polarity ? controls character length ? controls esci wakeup method ? controls idle character detection ? enables parity function ? controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the esci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable esci bit this read/write bit enables the esci and the esci baud rate generator. clearing ensci sets the scte and tc bits in esci status register 1 and disabl es transmitter interrupts. reset clears the ensci bit. 1 = esci enabled 0 = esci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit invert s all transmitted values including idle, break, start, and stop bits. m ? mode (character length) bit this read/write bit determines whether esci characters are eight or nine bits long (see table 14-5 ).the ninth bit can serve as a receiver wakeup signal or as a parity bit. reset clears the m bit. 1 = 9-bit esci characters 0 = 8-bit esci characters address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 14-10. esci control register 1 (scc1)
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 164 freescale semiconductor wake ? wakeup condition bit this read/write bit determines which condition wakes up the esci: a 1 (address mark) in the msb position of a received c haracter or an idle condition on t he rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the esci starts counting 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognit ion of an idle character. beginning the count after the stop bit avoids false idle character recognition , but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the esci parity function (see table 14-5 ). when enabled, the parity function inserts a parity bit in the msb position (see table 14-3 ). reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the esc i generates and checks for odd parity or even parity (see table 14-5 ). reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. table 14-5. character format selection control bits character format m pen:pty start bits data bits pa rity stop bits character length 0 0 x 1 8 none 1 10 bits 1 0 x 1 9 none 1 11 bits 0 1 0 1 7 even 1 10 bits 0 1 1 1 7 odd 1 10 bits 1 1 0 1 8 even 1 11 bits 1 1 1 1 8 odd 1 11 bits
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 165 14.8.2 esci control register 2 esci control register 2 (scc2): ? enables these cpu interrupt requests: ? scte bit to generate transmitter cpu interrupt requests ? tc bit to generate transmitter cpu interrupt requests ? scrf bit to generate receiver cpu interrupt requests ? idle bit to generate receiver cpu interrupt requests ? enables the transmitter ? enables the receiver ? enables esci wakeup ? transmits esci break characters sctie ? esci transmit interrupt enable bit this read/write bit enables the scte bit to generat e esci transmitter cpu interrupt requests. setting the sctie bit in scc2 enables the scte bit to generate cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate esci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? esci receive interrupt enable bit this read/write bit enables the scrf bit to generate esci receiver cpu interrupt requests. setting the scrie bit in scc2 enables the scrf bit to generate cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate esci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 14-11. esci control register 2 (scc2) :
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 166 freescale semiconductor te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the txd pin. if softw are clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowed when the enable esci bit (ensci) is clear. ensci is in esci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a 1. the 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the esci to send a break character instead of a preamble.
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 167 14.8.3 esci control register 3 esci control register 3 (scc3): ? stores the ninth esci data bit received and the ninth esci data bit to be transmitted. ? enables these interrupts: ? receiver overrun ? noise error ? framing error ? parity error r8 ? received bit 8 when the esci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the esci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the esci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. reset clears the t8 bit. orie ? receiver overrun interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the receiver overrun bit, or. reset clears orie. 1 = esci error cpu interrupt requests from or bit enabled 0 = esci error cpu interrupt requests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = esci error cpu interrupt requests from ne bit enabled 0 = esci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables esci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = esci error cpu interrupt requests from fe bit enabled 0 = esci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables esci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = esci error cpu interrupt requests from pe bit enabled 0 = esci error cpu interrupt requests from pe bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:u0000000 = unimplemented r = reserved u = unaffected figure 14-12. esci control register 3 (scc3)
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 168 freescale semiconductor 14.8.4 esci status register 1 esci status register 1 (scs1) contai ns flags to signal these conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error ? parity error scte ? esci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an esci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an esci transmitter cpu interrupt re quest. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an esci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is cleared automatically when data, preamble , or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? esci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the esci data register. scrf can generate an esci receiver cpu interrupt request. when the scrie bit in scc2 is set the scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. idle generates an esci error cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 14-13. esci status register 1 (scs1)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 169 a valid character that sets the scrf bit before an id le condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an esci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 14-14 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. figure 14-14. flag clearing sequence byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 170 freescale semiconductor nf ? receiver noise flag bit this clearable, read-only bit is set when the esc i detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is al so set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a 0 is accepted as the stop bit. fe generates an esci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected pe ? receiver parity error bit this clearable, read-only bit is set when the esci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected 14.8.5 esci status register 2 esci status register 2 (scs2) contai ns flags to signal these conditions: ? break character detected ? incoming data bkf ? break flag bit this clearable, read-only bit is set when the esci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become se t again only after 1s agai n appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the esci module or entering stop mode can show whethe r a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read:000000bkfrpf write: reset:00000000 = unimplemented figure 14-15. esci status register 2 (scs2)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 171 14.8.6 esci data register the esci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the esci data register. r7/t7:r0/t0 ? receive/transmit data bits reading address $0018 accesses the read-only rece ived data bits, r7:r0. writing to address $0018 writes the data to be transmitted, t7:t0. re set has no effect on the esci data register. note do not use read-modify-write instructions on the esci data register. 14.8.7 esci baud rate register the esci baud rate register (scbr) together with the esci prescaler register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. linr ? lin receiver bits this read/write bit selects the enhanced esci features for the local interconnect network (lin) protocol as shown in table 14-6 . reset clears linr. address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-16. esci data register (scdr) address: $0019 bit 7654321bit 0 read: r linr scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 14-17. esci baud rate register (scbr) table 14-6. esci lin control bits linr m functionality 0 x normal esci functionality 1 0 11-bit break detect enabled for lin receiver 1 1 12-bit break detect enabled for lin receiver
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 172 freescale semiconductor scp1 and scp0 ? esci baud rate register prescaler bits these read/write bits select the baud rate register prescaler divisor as shown in table 14-7 . reset clears scp1 and scp0. scr2?scr0 ? esci baud rate select bits these read/write bits select the esci baud rate divisor as shown in table 14-8 . reset clears scr2?scr0. 14.8.8 esci prescaler register the esci prescaler register (scpsc) together with the esci baud rate register selects the baud rate for both the receiver and the transmitter. note there are two prescalers available to adjust the baud rate. one in the esci baud rate register and one in the esci prescaler register. table 14-7. esci baud rate prescaling scp[1:0] baud rate register prescaler divisor (bpd) 00 1 01 3 10 4 11 13 table 14-8. esci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 address: $0009 bit 7654321bit 0 read: pds2 pds1 pds0 pssb4 pssb3 pssb2 pssb1 pssb0 write: reset:00000000 figure 14-18. esci prescaler register (scpsc)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 173 pds2?pds0 ? prescaler divisor select bits these read/write bits select the prescaler divisor as shown in table 14-9 . reset clears pds2?pds0. note the setting of ?000? will bypass this prescaler. it is not recommended to bypass the prescaler while ensci is set, because the switching is not glitch free. pssb4?pssb0 ? clock insertion select bits these read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in table 14-10 . reset clears pssb4?pssb0. table 14-9. esci prescaler division ratio ps[2:1:0] prescaler divisor (pd) 0 0 0 bypass this prescaler 001 2 010 3 011 4 100 5 101 6 110 7 111 8 table 14-10. esci prescaler divisor fine adjust pssb[4:3:2:1:0] prescaler divisor fine adjust (pdfa) 00000 0/32 = 0 0 0 0 0 1 1/32 = 0.03125 0 0 0 1 0 2/32 = 0.0625 0 0 0 1 1 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 table continued on next page
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 174 freescale semiconductor use the following formula to calculate the esci baud rate: where: f bus = bus frequency bpd = baud rate register prescaler divisor bd = baud rate divisor pd = prescaler divisor pdfa = prescaler divisor fine adjust table 14-11 shows the esci baud rates that can be generated with a 4.9152-mhz bus frequency. 0 1 1 1 1 15/32 = 0.46875 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.90625 1 1 1 1 0 30/32 = 0.9375 1 1 1 1 1 31/32 = 0.96875 table 14-10. esci prescaler divisor fine adjust (continued) pssb[4:3:2:1:0] prescaler divisor fine adjust (pdfa) baud rate f bus 64 bpd bd pd pdfa + () ----------------------------------------------------------------------------------- - =
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 175 table 14-11. esci baud rate selection examples ps[2:1:0] pssb[4:3:2:1:0] scp[1:0] prescaler divisor (bpd) scr[2:1:0] baud rate divisor (bd) baud rate (f bus = 4.9152 mhz) 000 xxxxx 00 1 000 1 76,800 111 00000 00 1 000 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.07 000 xxxxx 00 1 001 2 38,400 000 xxxxx 00 1 010 4 19,200 000 xxxxx 00 1 011 8 9600 000 xxxxx 00 1 100 16 4800 000 xxxxx 00 1 101 32 2400 000 xxxxx 00 1 110 64 1200 000 xxxxx 00 1 111 128 600 000 xxxxx 01 3 000 1 25,600 000 xxxxx 01 3 001 2 12,800 000 xxxxx 01 3 010 4 6400 000 xxxxx 01 3 011 8 3200 000 xxxxx 01 3 100 16 1600 000 xxxxx 01 3 101 32 800 000 xxxxx 01 3 110 64 400 000 xxxxx 01 3 111 128 200 000 xxxxx 10 4 000 1 19,200 000 xxxxx 10 4 001 2 9600 000 xxxxx 10 4 010 4 4800 000 xxxxx 10 4 011 8 2400 000 xxxxx 10 4 100 16 1200 000 xxxxx 10 4 101 32 600 000 xxxxx 10 4 110 64 300 000 xxxxx 10 4 111 128 150 000 xxxxx 11 13 000 1 5908 000 xxxxx 11 13 001 2 2954 000 xxxxx 11 13 010 4 1477 000 xxxxx 11 13 011 8 739 000 xxxxx 11 13 100 16 369 000 xxxxx 11 13 101 32 185 000 xxxxx 11 13 110 64 92 000 xxxxx 11 13 111 128 46
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 176 freescale semiconductor 14.9 esci arbiter the esci module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time det ection. the arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. the cpu can control operation mode via the esci arbiter control register (sciactl). 14.9.1 esci arbite r control register am1 and am0 ? arbiter mode select bits these read/write bits select the mode of the arbiter module as shown in table 14-12 . reset clears am1 and am0. alost ? arbitration lost flag this read-only bit indicates loss of arbitration. clear alost by writing a 0 to am1. reset clears alost. aclk ? arbiter counter clock select bit this read/write bit selects the arbiter counter clock source. reset clears aclk. 1 = arbiter counter is clocked with one half of t he esci input clock generated by the esci prescaler 0 = arbiter counter is clocked wi th one quarter of the bus clock afin? arbiter bit time measurement finish flag this read-only bit indicates bit ti me measurement has finished. clea r afin by writing any value to sciactl. reset clears afin. 1 = bit time measurement has finished 0 = bit time measurement not yet finished arun? arbiter counter running flag this read-only bit indicates the arbiter counter is running. reset clears arun. 1 = arbiter counter running 0 = arbiter counter stopped address: $000a bit 7654321bit 0 read: am1 alost am0 aclk afin arun arovfl ard8 write: reset:00000000 = unimplemented figure 14-19. esci arbiter control register (sciactl) table 14-12. esci arbiter selectable modes am[1:0] esci arbiter mode 0 0 idle / counter reset 0 1 bit time measurement 1 0 bus arbitration 1 1 reserved / do not use
esci arbiter mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 177 arovfl? arbiter counter overflow bit this read-only bit indicates an arbiter counter ov erflow. clear arovfl by writing any value to sciactl. writing 0s to am1 and am0 resets the counter keeps it in this idle state. reset clears arovfl. 1 = arbiter counter overflow has occurred 0 = no arbiter counter overflow has occurred ard8? arbiter counter msb this read-only bit is the msb of the 9-bit arbiter c ounter. clear ard8 by writing any value to sciactl. reset clears ard8. 14.9.2 esci arbite r data register ard7?ard0 ? arbiter least significant counter bits these read-only bits are the eight lsbs of the 9-bit arbiter counter. clear ard7?ard0 by writing any value to sciactl. writing 0s to am1 and am0 permanent ly resets the counter and keeps it in this idle state. reset clears ard7?ard0. 14.9.3 bit time measurement two bit time measurement modes, described here, are available acco rding to the state of aclk. 1. aclk = 0 ? the counter is clock ed with one quarter of the bus clock. the counter is started when a falling edge on the rxd pin is detected. the counter will be stopped on the next falling edge. arun is set while the counter is running, afin is set on the second falling edge on rxd (for instance, the counter is stopped). this mode is used to recover the received baud rate. see figure 14-21 . 2. aclk = 1 ? the counter is clocked with one half of the esci input clock generated by the esci prescaler. the counter is started when a 0 is detected on rxd (see figure 14-22 ). a 0 on rxd on enabling the bit time measurement with aclk = 1 leads to immediate start of the counter (see figure 14-23 ). the counter will be stopped on the next rising edge of rxd. this mode is used to measure the length of a received break. 14.9.4 arbitration mode if am[1:0] is set to 10, the arbiter module operates in arbitration mode. on every rising edge of sci_txd (output of the esci module, internal chip signal), the counter is started. when the counter reaches $38 (aclk = 0) or $08 (aclk = 1), rxd is statically sensed. if in this case, rxd is sensed low (for example, another bus is driving the bus dominant) alost is set. as long as alost is set, the txd pin is forced to 1, resulting in a seized transmission. if sci_txd is sensed 0 without having sensed a 0 befor e on rxd, the counter will be reset, arbitration operation will be restarted after the next rising edge of sci_txd. address: $000b bit 7654321bit 0 read: ard7 ard6 ard5 ard4 ard3 ard2 ard1 ard0 write: reset:00000000 = unimplemented figure 14-20. esci arbiter data register (sciadat)
enhanced serial communicatio ns interface (esci) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 178 freescale semiconductor figure 14-21. bit time measurement with aclk = 0 figure 14-22. bit time measurement with aclk = 1, scenario a figure 14-23. bit time measurement with aclk = 1, scenario b cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd with $20 arun = 1 afin = 1 out of sciadat cpu writes sciactl with $30 counter starts, arun = 1 counter stops, afin = 1 measured time cpu reads result out rxd of sciadat cpu writes sciactl counter starts, counter stops, measured time cpu reads result rxd out of sciadat afin = 1 arun = 1 with $30
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 179 chapter 15 system integration module (sim) 15.1 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim controls all microconr oller unit (mcu) activities. a bloc k diagram of the sim is shown in figure 15-1 . table 15-1 is a summary of the sim input/output (i/o) registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: ? bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control ? master reset control, including power-on reset (por) and computer operating properly (cop) timeout ? interrupt arbitration table 15-1 shows the internal signal names used in this section. table 15-1. signal name conventions signal name description cgmxclk selected clock source from internal clock generator module (icg) cgmout clock output from icg module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 180 freescale semiconductor figure 15-1. sim block diagram addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 193. read: rrrrrr sbsw r write: note reset:00000000 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 194. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 sim upper byte address register (subar) read: rrrrrrrr write: reset: figure 15-2. sim i/o register summary stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to icg) cgmout (from icg) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cgmxclk (from icg) 2 v dd internal pullup device forced monitor mode entry
sim bus clock control and generation mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 181 15.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, cgmout, as shown in figure 15-3 . this clock originates from either an external oscillat or or from the internal clock generator. figure 15-3. system clock signals 15.2.1 bus timing in user mode , the internal bus frequency is the internal clock generator output (cgmxclk) divided by four. $fe03 sim break flag control register (sbfcr) see page 195. read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) see page 189. read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) see page 190. read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) see page 190. read:000000if16if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved addr.register name bit 7654321bit 0 figure 15-2. sim i/o register summary (continued) icg cgmxclk 2 bus clock generators sim icg sim counter monitor mode clock select circuit iclk cs 2 a b s* cgmout *when s = 1, cgmout = b user mode generator eclk tbm prescaler tbmclk cop prescaler copclk
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 182 freescale semiconductor 15.2.2 clock startup fr om por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inac tive phase until after the 4096 cgmxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. 15.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows cgmxclk to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. see 15.6.2 stop mode. in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 15.3 reset and s ystem initialization the mcu has these reset sources: ? power-on reset module (por) ? external reset pin (rst ) ? computer operating properly module (cop) ? low-voltage inhibit module (lvi) ? illegal opcode ? illegal address ? forced monitor mode entry reset (modrst) all of these resets produce the vector $fffe:$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 15.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 15.7 sim registers. 15.3.1 external pin reset the rst pin circuit includes an internal pullu p device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that neither the por nor the lvi was the source of the reset. see table 15-2 for details. figure 15-4 shows the relative timing. figure 15-4. external reset timing rst iab pc vect h vect l cgmout
reset and system initialization mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 183 15.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. see figure 15-5 . an internal reset can be caused by an il legal address, illegal opcode, cop timeout, lvi, or por. see figure 15-6 . note for lvi or por resets, the sim c ycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 15-5 . the cop reset is asynchronous to the bus clock. the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. figure 15-5. internal reset timing figure 15-6. sources of internal reset 15.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 cgmxclk cycles. thirty-two cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. table 15-2. pin bit set timing reset recovery type actual number of cycles por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset modrst
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 184 freescale semiconductor at power-on, these events occur: ? a por pulse is generated. ? the internal reset signal is asserted. ? the sim enables cgmout. ? internal clocks to the cpu and modules are hel d inactive for 4096 cgmxclk cycles to allow stabilization of the oscillator. ?the rst pin is driven low during the oscillator stabilization time. ? the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. figure 15-7. por recovery 15.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 15.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the config1 register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode re set. the sim actively pulls down the rst pin for all internal reset sources. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff irst
sim counter mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 185 15.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bit in the sim reset status r egister (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 cgmxclk cycles. thirty-two cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 15.3.2.6 monitor mode entry module reset (modrst) the monitor mode entry module reset (modrst) asserts its output to the sim when monitor mode is entered in the condition where the reset vectors are erased ($ff). (see 19.3.1 functional description .) when modrst gets asserted, an internal rese t occurs. the sim actively pulls down the rst pin for all internal reset sources. 15.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter is 13 bits long. 15.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the clock generation module (cgm) to drive the bus clock state machine. 15.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the config1 register. if the ssrec bit is a 1, then the st op recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crys tal applications should use the full stop recovery time, that is, with ssrec cleared. 15.4.3 sim counter and reset states external reset has no effect on the sim counter. see 15.6.2 stop mode for details. the sim counter is free-running after all reset states. see 15.3.2 active resets from internal sources for counter control and internal reset recovery sequences.
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 186 freescale semiconductor 15.5 exception control normal, sequential program execution can be changed in three different ways: ? interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) ? reset ? break interrupts 15.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 15-8 shows interrupt entry timing. figure 15-9 shows interrupt recovery timing. figure 15-8 . interrupt entry timing figure 15-9. interrupt recovery timing interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). see figure 15-10 . module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit
exception control mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 187 figure 15-10. interrupt processing 15.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 15-11 demonstrates what happens when two interrupts are pending. if an interrupt no no yes no no yes no yes as many interrupts i bit set? from reset break i bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt?
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 188 freescale semiconductor is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. figure 15-11 . interrupt recognition example 15.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 15.5.1.3 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
exception control mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 189 interrupt status register 1 i6?i1 ? interrupt flags 1?6 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 table 15-3. interrupt sources priority interrupt source interrupt status register flag highest reset ? swi instruction ? irq pin i1 icg clock monitor i2 tim1 channel 0 i3 tim1 channel 1 i4 tim1 overflow i5 tim2 channel 0 i6 tim2 channel 1 i7 tim2 overflow i8 spi receiver full i9 spi transmitter empty i10 sci receive error i11 sci receive i12 sci transmit i13 keyboard i14 adc conversion complete i15 lowest timebase module i16 address: $fe04 bit 7654321bit 0 read:i6i5i4i3i2i1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 15-12. interrupt status register 1 (int1)
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 190 freescale semiconductor interrupt status register 2 i14?i7 ? interrupt flags 14?7 these flags indicate the presence of interrupt requests from the sources shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present interrupt status register 3 bits 7?2 ? always read 0 i16?i15 ? interrupt flags 16?15 these flags indicate the presence of an interrupt request from the source shown in table 15-3 . 1 = interrupt request present 0 = no interrupt request present 15.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 15.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see chapter 18 timer interface module (tim) ). the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 15.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). address: $fe05 bit 7654321bit 0 read: i14 i13 i12 i11 i10 i9 i8 i7 write:rrrrrrrr reset:00000000 r= reserved figure 15-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:000000i16i15 write:rrrrrrrr reset:00000000 r= reserved figure 15-14. interrupt status register 3 (int3)
low-power modes mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 191 protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 15.6 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 15.6.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 15-15 shows the timing for wait mode entry. figure 15-15. wait mode entry timing a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the config1 register is 0, then the computer operat ing properly module (cop) is enabled and remains active in wait mode. figure 15-16 and figure 15-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 192 freescale semiconductor figure 15-16. wait recovery from interrupt or break figure 15-17. wait recovery from internal reset 15.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the clock generator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is sele ctable using the ssrec bit in config1. if ssrec is set, stop recovery is reduced from the normal dela y of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. note all applications should use the full stop recovery time by clearing the ssrec bit unless oscenins top is set in config2. the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 15-18 shows stop mode entry timing. note to minimize stop current, all pins conf igured as inputs should be driven to a 1 or 0. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitsto pwait = rst pin, cpu interrupt or break interrupt interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
sim registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 193 figure 15-18. stop mode entry timing figure 15-19. stop mode recovery from interrupt 15.7 sim registers the sim has three memory-mapped registers. table 15-4 shows the mapping of these registers. 15.7.1 sim break st atus register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. table 15-4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r= reserved note: 1. writing a 0 clears sbsw. figure 15-20. sim break status register (sbsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 194 freescale semiconductor sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. 15.7.2 sim reset status register the srsr register contains flags that show the source of the latest reset. the status register will automatically clear after reading it. a power-on reset sets the por bit and clears all other bits in the register. all other reset sources set the individual fl ag bits but do not clear the register. more than one reset source can be flagged at any time depending on the c onditions at the time of the internal or external reset. for example, the por and lvi bits can both be set if the power supply has a slow rise time. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq v tst 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: reset:10000000 = unimplemented figure 15-21. sim reset status register (srsr)
sim registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 195 15.7.3 sim break flag control register the sim break control register contains a bit that e nables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 15-22. sim break flag control register (sbfcr)
system integration module (sim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 196 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 197 chapter 16 serial peripheral interface (spi) module 16.1 introduction this section describes the serial peripheral interfac e (spi) module, which allows full-duplex, synchronous, serial communications with peripheral devices. the text that follows describes the spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), mosi (master out slave in), and miso (master in/s lave out). the spi shares four i/o pins with four parallel i/o ports. 16.2 features features of the spi module include: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? four master mode frequencies (maximum = bus frequency 2) ? maximum slave mode frequency = bus frequency ? serial clock with programmable polarity and phase ? two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) ? mode fault error flag with cpu interrupt capability ? overflow error flag with cpu interrupt capability ? programmable wired-or mode ? i/o (input/output) port bit(s) software configurabl e with pullup device(s) if configured as input port bit(s) 16.3 functional description the spi module allows full-dupl ex, synchronous, serial communica tion between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt driven. if a port bit is configured for input, then an inter nal pullup device may be enabled for that port bit. the following paragraphs describe the operation of the spi module. refer to figure 16-2 for a summary of the spi i/o registers.
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 198 freescale semiconductor figure 16-1. block diagram highlighting spi block and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 199 figure 16-2. spi module block diagram addr.register name bit 7654321bit 0 $0010 spi control register (spcr) see page 213. read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) see page 214. read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) see page 216. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset r = reserved = unimplemented figure 16-3. spi i/o register summary transmitter cpu interrupt request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 busclk clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie spe spwom sprf spte ovrf m s pin control logic receive data register sptie spe internal bus modfen errie control modf spmstr mosi miso spsck ss
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 200 freescale semiconductor 16.3.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note in a multi-spi system, configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. see 16.12.1 spi control register . only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the sh ift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. see figure 16-4. figure 16-4. full-duplex master-slave connections the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see 16.12.2 spi status and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register (spdr) clears spte. 16.3.2 slave mode the spi operates in slave mode when spmstr is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be low. ss must remain low until the transmission is complete. see 16.6.2 mode fault error . in a slave spi module, data enters the shift register und er the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
transmission formats mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 201 the maximum frequency of the spsck fo r an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock t hat can be generated). th e frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its tr ansmit data register at least one bus cycle before the master starts the next transmission. otherwise, the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first e dge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. see 16.4 transmission formats . note spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 16.4 transmission formats during an spi transmission, data is simultaneously tr ansmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. 16.4.1 clock phase and polarity controls software can select any of four combinations of se rial clock (spsck) phase a nd polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (cpha) control bit selects one of tw o fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). 16.4.2 transmission format when cpha = 0 figure 16-5 shows an spi transmission in which cpha = 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slav e timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are di rectly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 202 freescale semiconductor input (ss ) is low, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see 16.6.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each byte transmitted as shown in figure 16-6 . when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss . any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. figure 16-5. transmission format (cpha = 0) figure 16-6. cpha/ss timing 16.4.3 transmission format when cpha = 1 figure 16-7 shows an spi transmission in which cpha = 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slav e. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is low, so that only the selected bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
transmission formats mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 203 slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not affecting the spi. (see 16.6.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first sps ck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 16-7. transmission format (cpha = 1) when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. 16.4.4 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr st arts a transmission. cpha has no effect on the delay to the start of the transmiss ion, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycl e begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1 :spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 16-8 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. since the spi clock is free-runni ng, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 16-8 . this delay is no longer than a single spi bi t time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for di v8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 204 freescale semiconductor figure 16-8. transmission start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = bus clock 2; earliest latest 2 possible start points spsck = bus clock 8; 8 possible start points earliest latest spsck = bus clock 32; 32 possible start points earliest latest spsck = bus clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock initiation delay from write spdr to transfer begin
queuing transm ission data mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 205 16.5 queuing tr ansmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transm itted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when spte is high. figure 16-9 shows the timing associated with doing back-to-back transmiss ions with the spi (spsck has cpha: cpol = 1:0). figure 16-9. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift r egister is the next data word to be transmitted. for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer emptie s into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. spte indicates when the next write can occur. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 206 freescale semiconductor 16.6 error conditions the following flags signal spi error conditions: ? overflow (ovrf) ? failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. ? mode fault error (modf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spi status and control register. 16.6.1 overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of th e next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7 (see figure 16-5 and figure 16-7 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector (see figure 16-12 .) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interrupt is enabled and the ovrf in terrupt is not, watch for an overflow condition. figure 16-10 shows how it is possible to miss an overflow. the first part of figure 16-10 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit c an be set in between the time that spscr and spdr are read. figure 16-10. missed read of overflow condition read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr
error conditions mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 207 in this case, an overflow can be missed easily. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 16-11 illustrates this process. g enerally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. figure 16-11. clearing sprf when ovrf interrupt is not enabled 16.6.2 mode fault error setting spmstr selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects sl ave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: ?the ss pin of a slave spi goes high during a transmission ?the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 16-12 .) it is not possible to enable modf or ovrf individual ly to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 208 freescale semiconductor in a master spi with the mode fault enable bit (modfe n) set, the mode fault flag (modf) is set if ss goes low. a mode fault in a master spi causes the following events to occur: ? if errie = 1, the spi generates an spi receiver/error cpu interrupt request. ? the spe bit is cleared. ? the spte bit is set. ? the spi state counter is cleared. ? the data direction register of the shared i/o port regains control of port drivers. note to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmi ssion continues until the spsck returns to its idle level following the shift of the last data bit. see see 16.4 transmission formats . note setting the modf flag does not clear the spmstr bit. spmstr has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. note when cpha = 0, a modf occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no spsck is sent to that slave. this happens because ss low indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), modf generates an spi re ceiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or re set the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note a high on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared.
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 209 16.7 interrupts four spi status flags can be enabled to generate cpu interrupt requests. see table 16-1 . reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables sprf to generate receiver cpu interrupt requests, regardless of the state of spe. see figure 16-12 . figure 16-12. spi interrupt request generation the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. the following sources in the spi status and control register can generate cpu interrupt requests: ? spi receiver full bit (sprf) ? sprf becomes set every time a byte transfers from the shift register to the receive data register. if the spi receiver interrupt enable bit, sprie, is also set, sprf generates an spi receiver/error cpu interrupt request. ? spi transmitter empty (spte) ? spte becomes set every time a byte transfers from the transmit data register to the shift register. if the spi transmit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. table 16-1. spi interrupts flag request spte ? transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf ? receiver full spi receiver cpu interrupt request (sprie = 1) ovrf ? overflow spi receiver/error interrupt request (errie = 1) modf ? mode fault spi receiver/e rror interrupt request (errie = 1) spte sptie sprf sprie spe cpu interrupt request cpu interrupt request spi transmitter spi receiver/error errie modf ovrf
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 210 freescale semiconductor 16.8 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is 0. whenever spe is 0, the following occurs: ? the spte flag is set. ? any transmission currently in progress is aborted. ? the shift register is cleared. ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is defaul ted back to being general-purpose i/o. these items are reset only by a system reset: ? all control bits in the spcr register ? all control bits in the spscr regist er (modfen, errie, spr1, and spr0) ? the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe betw een transmissions without having to set all control bits again when spe is set back high for t he next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that wa s configured as a master with the modfen bit set. 16.9 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 16.9.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are not accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interrupt requests by setting the error interrupt enable bit (errie). see 16.7 interrupts . 16.9.2 stop mode the spi module is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. 16.10 spi during break interrupts the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. bcfe in the sim break flag control r egister (sbfcr) enables software to clear status bits during the break state. see chapter 15 system integration module (sim). to allow software to clear status bits during a break interrupt, write a 1 to bcfe. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state.
i/o signals mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 211 to protect status bits during the break state, write a 0 to bcfe. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break wi th bcfe cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with bcfe cleared has no effect. 16.11 i/o signals the spi module has four i/o pins: ? miso ? master input/slave output ? mosi ? master output/slave input ? spsck ? serial clock ?ss ? slave select 16.11.1 miso (mas ter in/slave out) miso is one of the two spi module pins that transmits se rial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only w hen the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is 0 and its ss pin is low. to support a multiple-slave system, a high on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the mi so pin regardless of the state of the data direction register of the shared i/o port. 16.11.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full-duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mo si pin regardless of the st ate of the data direction register of the shared i/o port. 16.11.3 spsck (serial clock) the serial clock synchronizes data transmission between master and sl ave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the cl ock input. in full-duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port.
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 212 freescale semiconductor 16.11.4 ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 16.4 transmission formats .) since it is used to indicate the start of a transmission, ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 16-13 . when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of ss from creating a modf error. see 16.12.2 spi status and control register. figure 16-13. cpha/ss timing note a high on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all inco ming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunc tion with the modf flag to prevent multiple masters from driving mosi and spsck. (see 16.6.2 mode fault error.) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if modfen is 0 for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. when modfen is 1, ss is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. see table 16-2 . table 16-2. spi configuration spe spmstr modfen spi configuration function of ss pin 0x (1)) 1. x = don?t care x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 213 16.12 i/o registers three registers control and monitor spi operation: ? spi control register (spcr) ? spi status and control register (spscr) ? spi data register (spdr) 16.12.1 spi control register the spi control register: ? enables spi module interrupt requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? configures the spsck, mosi, and miso pins as open-drain outputs ? enables the spi module sprie ? spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests enabled 0 = sprf cpu interrupt requests disabled spmstr ? spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic stat e of the spsck pin betw een transmissions. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset cl ears the cpol bit. cpha ? clock phase bit this read/write bit controls the timing relati onship between the serial clock and spi data. (see figure 16-5 and figure 16-7 .) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be high between bytes. (see figure 16-13 .) reset sets the cpha bit. address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 r= reserved figure 16-14. spi control register (spcr)
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 214 freescale semiconductor spwom ? spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mos i, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsc k, mosi, and miso pins spe ? spi enable this read/write bit enables the spi module. cleari ng spe causes a partial reset of the spi. (see 16.8 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable this read/write bit enables cpu interrupt requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests enabled 0 = spte cpu interrupt requests disabled 16.12.2 spi status and control register the spi status and control register c ontains flags to si gnal these conditions: ? receive data register full ? failure to clear sprf bit before next byte is received (overflow error) ? inconsistent logic level on ss pin (mode fault error) ? transmit data register empty the spi status and control register also c ontains bits that perform these functions: ? enable error interrupts ? enable mode fault error detection ? select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte tr ansfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the sprie bit in the spi control register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 16-15. spi status and control register (spscr)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 215 errie ? error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests ovrf ? overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an ov erflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with modfen set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear modf by reading the spi stat us and control register (spscr) with modf set and then writing to the spi control regi ster (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte ? spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request if sptie in the spi control register is set also. note do not write to the spi data register unless spte is high. during an spte cpu interrupt, the cpu clears spt e by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen ? mode fault enable bit this read/write bit, when set, allows the modf flag to be set. if the modf flag is set, clearing modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is 0, then the ss pin is available as a general-purpose i/o. if the modfen bit is 1, then the ss pin is not available as a general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general-pu rpose i/o regardless of the value of modfen. see 16.11.4 ss (slave select). if the modfen bit is 0, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. see 16.6.2 mode fault error.
serial peripheral in terface (spi) module mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 216 freescale semiconductor spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-3 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calculate the spi baud rate: 16.12.3 spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes dat a into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can c ontain different values. see figure 16-2. r7?r0/t7?t0 ? receive/transmit data bits note do not use read-modify-write instructio ns on the spi data register since the register read is not the same as the register written. table 16-3. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 address: $0012 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-16. spi data register (spdr) baud rate = busclk bd
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 217 chapter 17 timebase module (tbm) 17.1 introduction this section describes the timebase module (tbm). the tbm will generate periodic interrupts at user selectable rates using a counter cloc ked by the external crystal clock. this tbm version uses 15 divider stages, eight of which are user selectable. 17.2 features features of the tbm include: ? software programmable 1-hz, 4-hz, 16-hz , 256-hz, 512-hz, 1024-hz, 2048-hz, and 4096-hz periodic interrupt using external 32.768-khz crystal ? user selectable oscillator clock source enable dur ing stop mode to allow periodic wakeup from stop 17.3 functional description note this module is designed for a 32.768-khz oscillator. this module can generate a periodic interrupt by dividing the clock tbmclk. the counter is initialized to all 0s when tbon bit is cleared. the counter, shown in figure 17-1 , starts counting when the tbon bit is set. when the counter overflows at the tap selected by tbr2:tbr0, the tbif bit gets set. if the tbie bit is set, an interrupt request is sent to the cpu. t he tbif flag is cleared by wr iting a 1 to the tack bit. the first time the tbif flag is set after enabli ng the timebase module, the interrupt is generated at approximately half of the overflow period. subsequent events occur at the exact period.
timebase module (tbm) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 218 freescale semiconductor figure 17-1. timebase block diagram 17.4 timebase register description the timebase has one register, the timebase control register (tbcr), which is used to enable the timebase interrupts and set the rate. tbif ? timebase interrupt flag this read-only flag bit is set when the timebase counter has rolled over. 1 = timebase interrupt pending 0 = timebase interrupt not pending address: $001c bit 7654321bit 0 read: tbif tbr2 tbr1 tbr0 0 tbie tbon r write: tack reset:00000000 = unimplemented r = reserved figure 17-2. timebase control register (tbcr) 2 sel 0 0 0 0 0 1 0 1 0 0 1 1 tbif tbr1 tbr0 tbie tbon r tack tbr2 1 0 0 1 0 1 1 1 0 1 1 1 tbmclk 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 16 32 64 128 2048 8192 32768 tbmint
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 219 tbr2:tbr0 ? timebase rate selection these read/write bits are used to select the rate of timebase interrupts as shown in table 17-1 . note do not change tbr2:tbr0 bits while the timebase is enabled (tbon = 1). tack ? timebase acknowledge the tack bit is a write-only bit and always reads as 0. writing a 1 to this bit clears tbif, the timebase interrupt flag bit. writing a 0 to this bit has no effect. 1 = clear timebase interrupt flag 0 = no effect tbie ? timebase interrupt enabled this read/write bit enables the timebase interrupt when the tbif bit becomes set. reset clears the tbie bit. 1 = timebase interrupt enabled 0 = timebase interrupt disabled tbon ? timebase enabled this read/write bit enables the timebase. timebase may be turned off to reduce power consumption when its function is not necessary. the counter can be initialized by clearing and then setting this bit. reset clears the tbon bit. 1 = timebase enabled 0 = timebase disabled and the counter initialized to 0s 17.5 interrupts the timebase module can interrupt the cpu on a regula r basis with a rate defined by tbr2:tbr0. when the timebase counter chain rolls over, the tbif flag is set. if the tbie bit is set, enabling the timebase interrupt, the counter chain overflow will generate a cpu interrupt request. interrupts must be acknowledged by writing a 1 to the tack bit. table 17-1. timebase rate selection for osc1 = 32.768 khz tbr2 tbr1 tbr0 divider timebase interrupt rate hz ms 0 0 0 32768 1 1000 0 0 1 8192 4 250 0 1 0 2048 16 62.5 0 1 1 128 256 ~ 3.9 1 0 0 64 512 ~2 1 0 1 32 1024 ~1 1 1 0 16 2048 ~0.5 1 1 1 8 4096 ~0.24
timebase module (tbm) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 220 freescale semiconductor 17.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 17.6.1 wait mode the timebase module remains active after execution of the wait instruction. in wait mode, the timebase register is not accessible by the cpu. if the timebase functions are not required during wa it mode, reduce the power consumption by stopping the timebase before enabling the wait instruction. 17.6.2 stop mode the timebase module may remain active after execution of the stop instruction if the oscillator has been enabled to operate during stop mode through the oscs topen bit in the config register. the timebase module can be used in this mode to gener ate a periodic wakeup from stop mode. if the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. in stop mode the timebase register is not accessible by the cpu. if the timebase functions are not required during st op mode, reduce the power consumption by stopping the timebase before enabling the stop instruction.
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 221 chapter 18 timer interface module (tim) 18.1 introduction this section describes the timer interface (tim) modul e. the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width- modulation functions. figure 18-1 is a block diagram of the tim. this particular mcu has two timer interfac e modules which are denoted as tim1 and tim2. figure 18-1. tim block diagram prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a t[1,2]ch0 t[1,2]ch1 interrupt logic port logic interrupt logic interrupt logic port logic
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 222 freescale semiconductor figure 18-2. block diagram highlighting tim blocks and pins single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
features mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 223 18.2 features features of the tim include: ? two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action ? buffered and unbuffered pulse-width-modulation (pwm) signal generation ? programmable tim clock input with 7-frequenc y internal bus clock prescaler selection ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tim counter stop and reset bits 18.3 pin name conventions the text that follows describes both timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch0 (timer channel 0) and t[1,2]ch1 (timer channel 1), where ?1? is used to indicate tim1 and ?2? is used to indicate tim2. the two tims share four i/o pins with four port d i/o port pins. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tch0 may refer generically to t1ch0 and t2ch0, and tch1 may refer to t1ch1 and t2ch1. 18.4 functional description figure 18-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programmable independently as input capture or output compare channels. if a channel is configured as input capture, then an internal pullup device may be enabled for that channel. see 12.5.3 port d input pullup enable register. figure 18-3 summarizes the timer registers. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc.
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 224 freescale semiconductor addr.register name bit 7654321bit 0 $0020 timer 1 status and control register (t1sc) see page 231. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer 1 counter register high (t1cnth) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer 1 counter register low (t1cntl) see page 232. read:bit 7654321bit 0 write: reset:00000000 $0023 timer 1 counter modulo register high (t1modh) see page 233. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer 1 counter modulo register low (t1modl) see page 233. read: bit 7654321bit 0 write: reset:11111111 $0025 timer 1 channel 0 status and control register (t1sc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer 1 channel 0 register high (t1ch0h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer 1 channel 0 register low (t1ch0l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer 1 channel 1 status and control register (t1sc1) see page 234. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer 1 channel 1 register high (t1ch1h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer 1 channel 1 register low (t1ch1l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b timer 2 status and control register (t2sc) see page 231. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-3. tim i/o register summary (sheet 1 of 2)
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 225 18.4.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 18.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter $002c timer 2 counter register high (t2cnth) see page 232. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $002d timer 2 counter register low (t2cntl) see page 232. read:bit 7654321bit 0 write: reset:00000000 $002e timer 2 counter modulo register high (t2modh) see page 233. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $002f timer 2 counter modulo register low (t2modl) see page 233. read: bit 7654321bit 0 write: reset:11111111 $0030 timer 2 channel 0 status and control register (t2sc0) see page 233. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0031 timer 2 channel 0 register high (t2ch0h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0032 timer 2 channel 0 register low (t2ch0l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset $0033 timer 2 channel 1 status and control register (t2sc1) see page 234. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0034 timer 2 channel 1 register high (t2ch1h) see page 236. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0035 timer 2 channel 1 register low (t2ch1l) see page 236. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 18-3. tim i/o register summary (sheet 2 of 2)
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 226 freescale semiconductor into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 18.4.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. 18.4.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 18.4.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 18.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares.
functional description mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 227 18.4.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 18-4 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 18.9.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. figure 18-4. pwm period and pulse width 18.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 18.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 228 freescale semiconductor ? when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 18.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to sy nchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 18.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. (see table 18-2 .) b. write 1 to the toggle-on-overflow bit, tovx.
interrupts mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 229 c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 18-2 .) note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the bu ffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 18.9.4 tim channel status and control registers .) 18.5 interrupts the following tim sources can generate interrupt requests: ? tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. ? tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 18.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 18.6.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction.
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 230 freescale semiconductor 18.6.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 18.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 15.7.3 sim break flag control register . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 18.8 i/o signals port d shares four of its pins with the tim. th e four tim channel i/o pins are t1ch0, t1ch1, t2ch0, and t2ch1 as described in 18.3 pin name conventions . each channel i/o pin is programmable independently as an input capture pin or an output compare pin. t1ch0 and t2ch0 can be configured as buffered output compare or buffered pwm pins. 18.9 i/o registers note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operation of the tim: ? tim status and control register (tsc) ? tim counter registers (tcnth:tcntl) ? tim counter modulo registers (tmodh:tmodl) ? tim channel status and control registers (tsc0, tsc1) ? tim channel registers (tch0h:tch0l, tch1h:tch1l)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 231 18.9.1 tim status and control register the tim status and control register (tsc): ? enables tim overflow interrupts ? flags tim overflows ? stops the tim counter ? resets the tim counter ? prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. address: t1sc, $0020 and t2sc, $002b bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-5. tim status and control register (tsc)
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 232 freescale semiconductor ps[2:0] ? prescaler select bits these read/write bits select one of the seven presca ler outputs as the input to the tim counter as table 18-1 shows. reset clears the ps[2:0] bits. 18.9.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 18-1. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 n o t a v a i l a b l e address: t1cnth, $0021 and t2cnth, $002c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 18-6. tim counter registers high (tcnth) address: t1cntl, $0022 and t2cntl, $002d bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented figure 18-7. tim counter registers low (tcntl)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 233 18.9.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof ) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. 18.9.4 tim channel status and control registers each of the tim channel status and control registers: ? flags input captures and output compares ? enables input capture and output compare interrupts ? selects input capture, output compare, or pwm operation ? selects high, low, or toggling output on output compare ? selects rising edge, falling edge, or any edge as the active input capture trigger ? selects output toggling on tim overflow ? selects 0% and 100% pwm duty cycle ? selects buffered or unbuffered output compare/pwm operation address: t1modh, $0023 and t2modh, $002e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 18-8. tim counter modulo register high (tmodh) address: t1modl, $0024 and t2modl, $002f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 18-9. tim counter modulo register low (tmodl) address: t1sc0, $0025 and t2sc0, $0030 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 18-10. tim channel 0 status and control register (tsc0)
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 234 freescale semiconductor chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. setting ms0b disables the channel 1 status and cont rol register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 18-2. 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. see table 18-2 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). address: t1sc1, $0028 and t2sc1, $0033 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 18-11. tim channel 1 status and control register (tsc1)
i/o registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 235 elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port d, and pin ptdx/tchx is available as a general-purpose i/o pin. table 18-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note before enabling a tim channel register for input capture operation, make sure that the ptd/tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 18-12 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 18-2. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x 1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 0 output compare or pwm software compare only 0 1 0 1 toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module (tim) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 236 freescale semiconductor figure 18-12. chxmax latency 18.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: t1ch0h, $0026 and t2ch0h, $0031 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-13. tim channel 0 register high (tch0h) address: t1ch0l, $0027 and t2ch0l $0032 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-14. tim channel 0 register low (tch0l) address: t1ch1h, $0029 and t2ch1h, $0034 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-15. tim channel 1 register high (tch1h) address: t1ch1l, $002a and t2ch1l, $0035 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-16. tim channel 1 register low (tch1l) output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 237 chapter 19 development support 19.1 introduction this section describes the break module, the mo nitor module (mon), and the monitor mode entry methods. 19.2 break module (brk) this section describes the break module (brk). th e break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: ? accessible input/output (i/o) registers during the break interrupt ? central processor unit (cpu) generated break interrupts ? software-generated break interrupts ? computer operating properly (cop ) disabling during break interrupts 19.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi). the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: ? a cpu generated address (the address in the program counter) matches the contents of the break address registers. ? software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt is generated. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller uni t (mcu) to normal operation. figure 19-2 shows the structure of the break module.
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 238 freescale semiconductor figure 19-1. block diagram highlighting brk and mon blocks single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user flash user ram ? 512 bytes monitor rom ? 304 bytes user flash vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains in tegrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module flash programming routines mc68hc908gt16 ? 15,872 bytes mc68hc908gt8 ? 7,680 bytes registers ? 64 bytes rom ? 720 bytes pta0/kbd0 (1)
break module (brk) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 239 figure 19-2. break module block diagram addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) see page 242. read:000100 sbsw 0 write:rrrrrrnoter reset:00010000 note: writing a 0 clear sbsw. $fe03 sim break flag control register (sbfcr) see page 242. read: bcferrrrrrr write: reset: 0 $fe09 break address register high (brkh) see page 241. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 241. read: bit 7654321bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 241. read: brke brka 000000 write: reset:00000000 = unimplemented r = reserved figure 19-3. i/o register summary iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 240 freescale semiconductor when the internal address bus matches the value writt en in the break address registers or when software writes a 1 to the brka bit in the break status and c ontrol register, the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction ? loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt timing is: ? when a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. ? when a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. ? when software writes a 1 to the brka bit, the break interrupt occurs just before the next instruction is executed. by updating a break address and clearing the brka bit in a break interrupt routine, a break interrupt can be generated continuously. caution a break address should be placed at the address of the instruction opcode. when software does not change the break address and clears the brka bit in the first break interrupt routi ne, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 19.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 15.7.3 sim break flag control register and the break interrupts subsection for each module. 19.2.1.2 tim1 and tim2 during break interrupts a break interrupt stops the timer counters. 19.2.1.3 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 19.2.2 break module registers these registers control and monitor operation of the break module: ? break status and control register (brkscr) ? break address register high (brkh) ? break address register low (brkl) ? sim break status register (sbsr) ? sim break flag control register (sbfcr)
break module (brk) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 241 19.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match 19.2.2.2 break address registers the break address registers (brkh and brkl) contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-4. break status and control register (brkscr) address: $fe09 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 19-5. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 19-6. break address register low (brkl)
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 242 freescale semiconductor 19.2.2.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. this register is only used in emulation mode. sbsw ? sim break stop/wait sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt 19.2.2.4 break flag control register the sim break flag control register (sbfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 19-7. sim break status register (sbsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 19-8. sim break flag control register (sbfcr)
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 243 19.3 monitor module (mon) the monitor module allows debugging and programmin g of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features of the monitor module include: ? normal user-mode pin functionality ? one pin dedicated to serial communication betwe en monitor read-only memory (rom) and host computer ? standard mark/space non-return-to-zero (nrz) communication with host computer ? execution of code in random-a ccess memory (ram) or flash ? flash memory security feature (1) ? flash memory programming interface ? external 4.92 mhz or 9.83 mhz clock used to generate internal frequency of 2.4576 mhz ? optional icg mode of operation (no external clock or high voltage) ? monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) ? normal monitor mode entry if high voltage is applied to irq 19.3.1 functional description figure 19-9 shows a simplified monitor mode entry flowchart. the monitor rom receives and executes commands from a host computer. figure 19-10, figure 19-11 , and figure 19-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. the monitor code has been updated from previous ve rsions of the monitor code to allow the icg to generate the internal clock. this option, which is selected when irq is held low out of reset, is intended to support serial communication/ programming at 960 0 baud in monitor mode by using the icg, and the icg user trim value icgtr5 (if programmed) to generate the desired internal frequency (2.4576 mhz). if icgtr5 is not programmed (i.e., the value is $ff) then the icg will operate at a nominal (untrimmed) 2.45 mhz and communications will be nominally at 9600 baud but the untrimmed rate may cause difficulties with hosts which cannot automatically adjust their data rates to match. since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $ffff) be cause entry into monitor mode in this case requires v tst on irq . 1. no security feature is absolutely secure. however, freescale?s strategy is to make reading or copying the flash difficult fo r unauthorized users.
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 244 freescale semiconductor figure 19-9. simplified monitor mode entry flowchart monitor mode entry por reset pta0 = 1, ptc0 = 1, ptc1 = 0, and ptc3 = 1? irq = v tst ? pta0 = 1, reset blank? yes no yes no forced monitor mode normal user mode normal monitor mode factory use only no no send 8 bytes security is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 19-1 debugging and flash programming (if flash is enabled)
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 245 figure 19-10. forced monitor mode (low) figure 19-11. forced monitor mode (high) rst irq pta0 2 k 0.1 f osc2 n.c. osc1 n.c. 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 0.1 f max232 c1+ c1? v+ v? 5 4 1 f c2+ c2? v dd 1 f + v tst 1 2 3 4 5 6 74hc125 74hc125 10 k n.c. n.c. ptc0 ptc3 n.c. ptc1 v ss v ssa 0.1 f v dda v dd + + 3 1 1 f + v dd v cc gnd 1 f rst irq pta0 0.1 f osc2 n.c. osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 0.1 f max232 v+ v? v dd 1 f + v tst 1 2 3 4 5 6 74hc125 74hc125 10 k n.c. n.c. ptc0 ptc3 n.c. ptc1 v ss v ssa 0.1 f v dda v dd + 9.8304 mhz clock n.c. c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + v dd v cc gnd 1 f
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 246 freescale semiconductor figure 19-12. standard monitor mode table 19-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode must be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. if $fffe and $ffff does not contain $ff (programmed state): ? the external clock is 4.9152 mhz with ptc3 low or 9.8304 mhz with ptc3 high ?irq = v tst 2. if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq = v dd (this can be implemented through the internal irq pullup) 3. if $fffe and $ffff contain $ff (erased state): ?irq = v ss (icg is selected, no external clock required) once out of reset, the mcu waits for the host to send eight security bytes (see 19.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. note the pta0 pin must remain high for 24 bus cycles after the rst pin goes high to enter monitor mode properly. + 10 k 10 k v dd 2 k rst irq pta0 0.1 f osc2 n.c. osc1 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 0.1 f max232 v+ v? v dd 1 f + v tst 1 2 3 4 5 6 74hc125 74hc125 10 k ptc0 ptc3 ptc1 v ss v ssa 0.1 f v dda v dd 9.8304 mhz clock 1 k 9.1 v c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + v dd v cc gnd 1 f
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 247 19.3.1.1 normal monitor mode when v tst is applied to irq and ptc3 is low upon monitor mode entry, the bus frequency is a divide-by-two of the input cl ock. if ptc3 is high with v tst applied to irq upon monitor mode entry, the bus frequency will be a divide-by-four of the input cl ock. holding the ptc3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v tst is applied to irq . in this event, the cgmout frequency is equal to the cgmx clk frequency, and the osc1 input directly generates internal bus clocks. in this case, the os c1 signal must have a 50% duty cycle at maximum bus frequency. table 19-1. monitor mode signal requirements and options mode irq rst reset vector serial comm. mode selection divider icg cop communication speed pta0 ptc0 ptc1 ptc3 external clock bus frequency baud range normal monitor v tst v dd or v ss x1100offdisabled 4.9152 mhz 2.4576 mhz 9600 v tst v dd or v ss x1101offdisabled 9.8304 mhz 2.4576 mhz 9600 forced monitor v dd v dd $ffff (blank) 1 x x x off disabled 9.8304 mhz 2.4576 mhz 9600 v ss v dd $ffff (blank) 1 x x x on disabled x nominal 2.4576 mhz nominal 9600 user v dd or v ss v dd or v ss not $ffff xxxxxenabledx x x mon08 function [pin no.] v tst [6] rst [4] ? com [8] mod0 [12] mod1 [14] div4 [16] ?? osc1 [13] ?? 1. pta0 must have a pullup resistor to vdd in monitor mode. 2. communication speed in the table is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus frequency / 256. 3. external clock is a 4.1952 mhz or 9.8304 mhz canned oscillator on osc1. 4. x = don?t care. 5. mon08 pin refers to p&e microcomputer syst ems? monout-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 nc nc 11 12 ptc0 osc1 13 14 ptc1 v dd 15 16 ptc3
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 248 freescale semiconductor if monitor mode was entered with v tst on irq , then the cop is disabled as long as v tst is applied to either irq or rst . this condition states that as long as v tst is maintained on the irq pin after entering monitor mode, or if v tst is applied to rst after the initial reset to get into monitor mode (when v tst was applied to irq ), then the cop will be disabled. in the latter situation, after v tst is applied to the rst pin, v tst can be removed from the irq pin in the interest of freeing the irq for normal functionality in monitor mode. 19.3.1.2 forced monitor mode if entering monitor mode without high voltage on irq (where applied voltage is either v dd or v ss ), then all port c pin requirements and conditions, including the ptc3 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. if irq = v dd on monitor mode entry, an external oscillator of 9.8304 mhz is required for a 9600 baud rate. if irq = v ss on monitor mode entry, the icg generates a 9600 baud rate using the trimmed icg value in the icgtr5 register. if the icgtr5 register is blank, the baud rate will be a nominal 9600 baud which may not be adequate for standard pc serial communication. when forced monitor mode is entered, the cop is always disabled regardless of the state of irq or rst . note if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial por reset. once the part has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. 19.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. note exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (por). pulling rst low will not exit monitor mode in this situation. table 19-2 summarizes the differences be tween user mode and monitor mode. table 19-2. mode differences modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 249 19.3.1.4 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. transmit and receive baud rates must be identical. figure 19-13. monitor data format 19.3.1.5 break signal a start bit (0) followed by nine 0 bits is a break signal. when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 19-14. break transaction 19.3.1.6 baud rate the communication baud rate is controlled by the external clock or icg upon entry into monitor mode. table 19-1 lists external frequencies required to achiev e a standard baud rate of 9600 bps. the effective baud rate is the bus frequency divided by 256. 19.3.1.7 commands the monitor rom firmware uses these commands: ? read (read memory) ? write (write memory) ? iread (indexed read) ? iwrite (indexed write) ? readsp (read stack pointer) ? run (run user program) the monitor rom firmware echoes each received byte back to the pta0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit 2-stop bit delay before zero echo
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 250 freescale semiconductor figure 19-15. read transaction figure 19-16. write transaction a brief description of each monitor mode command is given in table 19-3 through table 19-7 . table 19-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence read read echo from host address high address high address low address low data return 13 , 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32 , 3 1 = echo delay, approximately 2 bit times read read echo sent to monitor address high address high address low data return address low
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 251 a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 19-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 19-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand none data returned returns contents of next two addresses opcode $1a command sequence table 19-6. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence write write echo from host address high address high address low address low data data iread iread echo from host data return data readsp readsp echo from host sp return sp high low
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 252 freescale semiconductor the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 19-17. stack pointer at monitor mode entry 19.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. see figure 19-18 . table 19-7. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence run run echo from host condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7
monitor module (mon) mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 253 upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and tr ying to execute code from flash causes an illegal address reset. after receiving the eight security byte s from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. figure 19-18. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $40 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 cgmxclk cycles 5 1 4 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 4 = wait 1 bit time before sending next byte 4 from host from mcu 1 = echo delay, approximately 2 bit times 5 = wait until the monitor rom runs
development support mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 254 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 255 chapter 20 electrical specifications 20.1 introduction this section contains electrical and timing specifications. 20.2 absolute maximum ratings maximum ratings are the extreme limits to which t he microcontroller unit (mcu) can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 20.5 5.0-v dc electrical characteristics for guaranteed operating conditions . note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to + 6.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v maximum current per pin excluding those specified below i 15 ma maximum current for pins pta5-pta7, ptd4 i pta5?pta7 20 ma maximum current for pins ptc0?ptc4 i ptc0?ptc4 25 ma maximum current into v dd i mvdd 150 ma maximum current out of v ss i mvss 150 ma storage temperature t stg ?55 to +150 c
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 256 freescale semiconductor 20.3 functional operating range 20.4 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to +85 c operating voltage range v dd 3.0 10% 5.0 10% v characteristic symbol value unit thermal resistance 42-pin sdip 44-pin qfp ja 60 95 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c ) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c) + p d 2 ja w / c average junction temperature t j t a + (p d ja ) c
5.0-v dc electrical characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 257 20.5 5.0-v dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?2.0 ma) all i/o pins (i load = ?10.0 ma) all i/o pins (i load = ?20.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.8 v dd ? 1.5 v dd ? 1.5 ? ? ? ? ? ? ? ? ? ? ? ? 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 20ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.4 1.5 1.5 50 50 100 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ?v dd v input low voltage all ports, irq , rst , osc1 v il v ss ?0.2 v dd v dc injection current, all ports (3) 3. some disturbance of the adc accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. this parameter is guaranteed by characterization. i inj ? 2.0 ? + 2.0 ma total dc current injection (sum of all i/o) (3) i injtot ? 25 ? +25 ma i/o ports hi-z leakage current (4) 4. pullups and pulldowns are disabled. port b leakage is specified in 20.16 adc characteristics . i il ?? 10 a input current i in ?? 1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 45 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 3.90 4.25 4.50 v low-voltage inhibit, trip rising voltage v tripr 4.20 4.35 4.60 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?100 ?mv por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0 ? 100 mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0 700 800 mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.035 ? ? v/ms
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 258 freescale semiconductor 20.6 3.0-v dc electrical characteristics characteristic (1) 1. v dd = 3.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?0.6 ma) all i/o pins (i load = ?4.0 ma) all i/o pins (i load = ?10.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.3 v dd ? 1.0 v dd ?1.0 ? ? ? ? ? ? ? ? ? ? ? ? 30 30 60 v v v ma ma ma output low voltage (i load = 0.5 ma) all i/o pins (i load = 5.0 ma) all i/o pins (i load = 10.0 ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.3 1.0 1.0 30 30 60 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ?v dd v input low voltage all ports, irq , rst , osc1 v il v ss ?0.3 v dd v dc injection current, all ports (3) 3. some disturbance of the adc accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. this parameter is guaranteed by characterization. i inj ? 2.0 ? + 2.0 ma total dc current injection (sum of all i/o) (3) i injtot ? 25 ? +25 ma i/o ports hi-z leakage current (4) 4. pullups and pulldowns are disabled. i il ?? 10 a input current i in ?? 1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 45 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 2.45 2.60 2.70 v low-voltage inhibit, trip rising voltage v tripr 2.55 2.66 2.80 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?60 ?mv por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0 ? 100 mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0 700 800 mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms
supply current characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 259 20.7 supply current characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted voltage bus frequency (mhz) symbol typ (2) 2. typical values reflect average measurements at 25 c only. max unit run mode v dd supply current (3) 3. run (operating) i dd measured using external square wave clock source (f osc = 32 mhz for 5 v and f osc =16mhz for 3 v). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. measured with all modules enabled. 5.0 3.0 8 4 r idd 15 4.5 20 8 ma wait mode v dd supply current (4) 4. wait i dd measured using external square wave clock source (f osc = 32 mhz for 5 v and f osc = 16 mhz for 3 v). all inputs 0.2 v from rail. no dc loads. less than 1 00 pf on all outputs. all po rts configured as inputs. measured with icg and lvi enabled. 5.0 3.0 8 4 w idd 4 1.5 8 4 ma stop mode v dd supply current (5) 25c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) 5. stop i dd is measured with osc1 = v ss . 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 32 mhz for 5 v and f osc =16mhz for 3 v). 5.0 s idd 1 20 300 50 500 5 ? ? ? ? a stop mode v dd supply current (5) 25c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) 3.0 s idd 2 12 200 30 300 3 ? ? ? ? a
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 260 freescale semiconductor 20.8 5-v control timing figure 20-1. rst and irq timing 20.9 3-v control timing figure 20-2. rst and irq timing characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. symbol min max unit internal operating frequency f op (f bus ) ?8mhz internal clock period (1/f op )t cyc 122 ? ns rst input pulse width low t rl 50 ? ns irq interrupt pulse width low (edge-triggered) t ilih 50 ? ns irq interrupt pulse period t ilil note (2) 2. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ? t cyc characteristic (1) 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency f op (f bus ) ?4mhz internal clock period (1/f op )t cyc 244 ? ns rst input pulse width low t rl 125 ? ns irq interrupt pulse width low (edge-triggered) t ilih 125 ? ns irq interrupt pulse period t ilil note (2) 2. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ? t cyc rst irq t rl t ilih t ilil rst irq t rl t ilih t ilil
internal oscillator characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 261 20.10 internal oscill ator characteristics 20.11 external oscillator characteristics characteristic (1) 1. v dd = 5.5 vdc to 2.7 vdc, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ max unit internal oscillator base frequency (2), (3) 2. internal oscillator is selectable through softwa re for a maximum frequency. actual frequency will be multiplier (n) x base frequency. 3. f bus = (f intosc / 4) x n when internal clock source selected f intosc 230.4 307.2 384 khz internal oscillator tolerance f osc_tol ?25 ? +25 % internal oscillator multiplier (4) 4. multiplier must be chosen to limit the maximu m bus frequency of 4 mhz for 2.7-v operation and 8 mhz for 4.5-v operation. n1?1 2 7? characteristic (1) 1. v dd = 5.5 to 2.7 vdc, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ max unit external clock option (2)(3) with icg clock disabled with icg clock enabled extslow = 1 (4) extslow = 0 (4) 2. setting extclken configuration option enables osc1 pin for external clock square-wave input. 3. no more than 10% duty cycle deviation from 50% 4. extslow configuration option configures external oscillator for a slow speed crystal and sets the clock monitor circuits of the icg module to expect an external clock frequency that is higher/lower than the internal oscillator base frequency, f intosc. f extosc dc (5) 60 307.2 k 5. some modules may require a minimum frequency greater t han dc for proper operation. s ee appropriate table for this information. ? ? ? 32 m (6) 307.2 k 32 m (6) 6. mcu speed derates from 32 mhz at v dd = 4.5 vdc to 16 mhz at v dd = 2.7 vdc. hz external crystal options (7)(8) extslow = 1 (4) extslow = 0 (4) 7. setting extclken and extxtalen conf iguration options enables osc1 and osc2 pins for external crystal option. 8. f bus = (f extosc / 4) when external clock source is selected. f extosc 30 k 1 m ? ? 100 k 10 m hz crystal load capacitance (9) 9. consult crystal ve ndor data sheet, see figure 7-4. external clock generator block diagram . c l ???pf crystal fixed capacitance (9) c 1 ? 2 x c l ?pf crystal tuning capacitance (9) c 2 ? 2 x c l ?pf feedback bias resistor (9) r b ?10?m series resistor (9)(10) 10. not required for high-frequency crystals r s ???m
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 262 freescale semiconductor 20.12 trimmed accuracy of the internal clock generator the unadjusted frequency of the low-frequency base clock (ibase), when the comparators in the frequency comparator indicate zero error, can vary as much as 25% due to process, temperature, and voltage. the trimming capability ex ists to compensate for process effects. the remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting). these effects are designed to be minimal, however variation does occur. better performance is seen at 3 v and lower settings of n. 20.12.1 2.7-volt to 3.3- volt trimmed internal cl ock generator characteristics 20.12.2 4.5-volt to 5.5- volt trimmed internal cl ock generator characteristics characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c 2. absolute value of variation in icg output frequency, trimmed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ?2.54.0% variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.03 0.05 %/c variation over voltage (3), (5) 25c ?40 c to 85 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? 0.5 0.7 2.0 2.0 %/v characteristic (1) 1. these specifications concern long -term frequency variation. each meas urement is taken over a 1-ms period. symbol min typ max unit absolute trimmed internal oscillator tolerance (2), (3) ?40 c to 85 c 2. absolute value of variation in icg output frequency, trimmed at nominal v dd and temperature, as temperature and v dd are allowed to vary for a single given setting of n. 3. specification is char acterized but not tested. f abs_tol ?4.04.0% variation over temperature (3), (4) 4. variation in icg output frequency for a fixed n and voltage v ar_temp ? 0.05 0.08 %/c variation over voltage (3), (5) 25c ?40 c to 85 c 5. variation in icg output frequency for a fixed n v ar_volt ? ? 1.0 1.0 2.0 2.0 %/v
output high-voltage characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 263 20.13 output high-voltage characteristics figure 20-3. typical high-side driver characteristics ? port pta7?pta0 (v dd = 4.5 vdc) figure 20-4. typical high-side driver characteristics ? port pta7?pta0 (v dd = 2.7 vdc) figure 20-5. typical high-side driver characteristics ? port ptc4?ptc0 (v dd = 4.5 vdc) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) ?40 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 v oh > v dd ?0.8 v @ i oh = ?2.0 ma v oh > v dd ?1.5 v @ i oh = ?10.0 ma ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?0.3 v @ i oh = ?0.6 ma v oh > v dd ?1.0 v @ i oh = ?10.0 ma ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) ?40 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 v oh > v dd ?1.5 v @ i oh = ?20.0 ma
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 264 freescale semiconductor figure 20-6. typical high-side driver characteristics ? port ptc4?ptc0 (v dd = 2.7 vdc) figure 20-7. typical high-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 5.5 vdc) figure 20-8. typical high-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 2.7 vdc) ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?1.0 v @ i oh = ?10.0 ma ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?40 0 25 i oh (ma) ?90 v oh (v) 3 3.4 3.6 3.8 4.0 4.2 3.2 85 ?80 4.6 4.4 v oh > v dd ?0.8 v @ i oh = ?2.0 ma v oh > v dd ?1.5 v @ i oh = ?10.0 ma ?25 ?20 ?15 ?10 ?5 0 ?40 0 25 i oh (ma) 1.3 1.7 1.9 2.1 2.3 2.5 1.5 85 v oh (v) v oh > v dd ?0.3 v @ i oh = ?0.6 ma v oh > v dd ?1.0 v @ i oh = ?4.0 ma
output low-voltag e characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 265 20.14 output low-voltage characteristics figure 20-9. typical low-side driver characteristics ? port pta7?pta0 (v dd = 5.5 vdc) figure 20-10. typical low-side driver characteristics ? port pta7?pta0 (v dd = 2.7 vdc) figure 20-11. typical low-side driver characteristics ? port ptc4?ptc0 (v dd = 4.5 vdc) 5 10 15 20 25 30 35 ?40 0 25 i ol (ma) 0 v ol (v) 0 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.4 v @ i ol = 1.6 ma v ol < 1.5 v @ i ol = 10.0 ma 2 4 6 8 10 12 14 ?40 0 25 i ol (ma) 0 v ol (v) 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.3 v @ i ol = 0.5 ma v ol < 1.0 v @ i ol = 6.0 ma 10 20 30 40 50 60 i ol (ma) 0 v ol (v) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?40 0 25 85 v ol < 1.5 v @ i ol = 20 ma
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 266 freescale semiconductor figure 20-12. typical low-side driver characteristics ? port ptc4?ptc0 (v dd = 2.7 vdc) figure 20-13. typical low-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 5.5 vdc) figure 20-14. typical low-side driver characteristics ? ports ptb7?ptb0, ptc6?ptc5, ptd7?ptd0, and pte1?pte0 (v dd = 2.7 vdc) 5 10 15 20 25 30 ?40 0 25 i ol (ma) 0 v ol (v) 0.40.60.81.01.2 0.2 85 1.4 1.6 v ol < 0.8 v @ i ol = 10 ma 5 10 15 20 25 30 35 ?40 0 25 i ol (ma) 0 v ol (v) 0 0.4 0.6 0.8 1.0 1.2 0.2 85 1.4 1.6 v ol < 0.4 v @ i ol = 1.6 ma v ol < 1.5 v @ i ol = 10.0 ma 2 4 6 8 10 12 14 ?40 0 25 i ol (ma) 0 v ol (v) 0.2 0.4 0.6 0.8 1.0 0 85 1.2 1.6 1.4 v ol < 0.3 v @ i ol = 0.5 ma v ol < 1.0 v @ i ol = 6.0 ma
typical supply currents mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 267 20.15 typical supply currents figure 20-15. typical operating i dd , with all modules turned on (?40 c to 85 c) figure 20-16. typical wait mode i dd , with all modules disabled (?40 c to 85 c) 0 2 4 6 8 10 12 0123456789 5.5 v 3.6 v f bus (mhz) i dd (ma) 14 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 01 23 456 78 5.5 v 3.6 v i dd (ma) f bus (mhz)
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 268 freescale semiconductor 20.16 adc characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v dda = 5.0 vdc 10%, v ssa = 0 vdc, v refh = 5.0 vdc 10%, v refl = 0 symbol min max unit comments supply voltage v dda 2.7 (v dd min) 5.5 (v dd max) v v dda should be tied to the same potential as v dd via separate traces. input voltages v adin 0v dda v resolution b ad 88b i t s absolute accuracy (v refl = 0 v, v refh = v dda = 5 v 10%) a ad ? 1 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v refl v refh vv ssa v adin v dda power-up time t adpu 16 t aic cycles adc voltage reference high v refh v ssa ? 0.1 v dda + 0.1 v v refl v refh adc voltage reference low v refl v ssa ? 0.1 v dda + 0.1 v v refl v refh conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k adversely affect internal rc charging time during input sampling. t ads 5?t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 01 hex v in = v refl full-scale reading (3) f adi fe ff hex v in = v refh input capacitance c adi ? 8 pf not tested input leakage (4) port b 4. the external system error caused by in put leakage current is approximately equal to the product of r source and input current. ?? 1 a
5.0-v spi characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 269 20.17 5.0-v spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 20-17 and figure 20-18 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1?t cyc 3 enable lag time t lag(s) 1?t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?25 1/2 t cyc ?25 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 30 30 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 30 30 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 40 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?4 0n s 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 50 50 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 270 freescale semiconductor 20.18 3.0-v spi characteristics diagram number (1) 1. numbers refer to dimensions in figure 20-17 and figure 20-18 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 1?t cyc 3 enable lag time t lag(s) 1?t cyc 4 clock (spsck) high time master slave t sckh(m) t sckh(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) t cyc ?35 1/2 t cyc ?35 64 t cyc ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 40 40 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 40 40 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 50 50 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?5 0n s 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 60 60 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 0 ? ? ns ns
3.0-v spi characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 271 figure 20-17. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 272 freescale semiconductor figure 20-18. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1
timer interface module characteristics mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 273 20.19 timer interface module characteristics 20.20 memory characteristics characteristic symbol min max unit input capture pulse width t tih , t til 1?t cyc characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 8k ? 8m hz flash page erase time <1 k cycles >1 k cycles t erase 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase 4??ms flash pgm/erase to hven set up time t nvs 10 ? ? s flash high-voltage hold time t nvh 5?? s flash high-voltage hold time (mass erase) t nvhl 100 ? ? s flash program hold time t pgs 5?? s flash program time t prog 30 ? 40 s flash return to read time t rcv (2) 2. t rcv is defined as the time it needs before the flash can be re ad after turning off the high voltage charge pump, by clearing hven to 0. 1?? s flash cumulative program hv period t hv (3) 3. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 32) t hv maximum. ?? 4ms flash program endurance (4) 4. typical endurance was evaluated for this product family. for additional information on how freescale defines typical endurance , please refer to engineering bulletin eb619. ? 10k 100k ? cycles flash data retention time (5) 5. typical data retention values are bas ed on intrinsic capability of the technology measured at high temperature and de-rated to 25c using the arrhenius equation. for add itional information on how freescale defines typical data retention , please refer to engineering bulletin eb618. ?1 51 0 0?y e a r s
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 274 freescale semiconductor
mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 275 chapter 21 ordering information and mechanical specifications 21.1 introduction this section contains ordering numbers for th e mc68hc908gt16 and mc68hc908gt8 and gives the dimensions for: ? 42-pin shrink dual in-line package (case 858-01) ? 44-pin plastic quad flat pack (case 824a-01) the following figures show the latest package drawings at the time of th is publication. to make sure that you have the latest package specif ications, contact your local frees cale semiconductor sales office. 21.2 mc order numbers figure 21-1. device numbering system 21.3 package dimensions refer to the following pages for detailed package dimensions. table 21-1. mc order numbers mc order number operating temperature range package mc908gt16cb ?40 c to +85 c 42-pin sdip mc908gt16cfb ?40 c to +85 c 44-pin qfp mc908gt8cb ?40 c to +85 c 42-pin sdip MC908GT8CFB ?40 c to +85 c 44-pin qfp m c 9 0 8 g t x x x x x e family package designator temperature range pb free

mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 281 appendix a mc68hc08gt16 a.1 introduction this section introduces the mc68hc08gt16, the rom part equivalent to the mc68hc908gt16. the entire data book apply to this rom device, with exceptions outlined in this appendix. a.2 mcu block diagram figure a-1 shows the block diagram of the mc68hc08gt16. a.3 memory map the mc68hc08gt16 has 15,872 bytes of user rom fr om $c000 to $fdff, and 36 bytes of user rom vectors from $ffdc to $ffff. on the mc68hc908gt16, these memory locations are flash memory. table a-2 shows the memory map of the mc68hc08gt16. a.4 reserved registers the two registers at $fe08 and $ff7e are reserved locations on the mc68hc08gt16. on the mc68hc908gt16, these two locations are the fl ash control register and the flash block protect register respectively. table a-1. summary of mc68hc08gt16 and mc68hc908gt16 differences mc68hc08gt16 mc68hc908gt16 memory ($c000?$fdff) 15,872 bytes rom 15,872 bytes flash user vectors ($ffdc?$ffff) 36 bytes rom 36 bytes flash registers at $fe08 and $ff7e not used; locations are reserved. flash related registers. $fe08 ? flcr $ff7e ? flbpr registers at $f f80 and $ff81 icg trim registers with fixed values. icg user trim registers. monitor rom used for testing purposes only. used fo r testing and flash programming/erasing.
mc68hc08gt16 mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 282 freescale semiconductor figure a-1. mc68hc08gt16 block diagram single breakpoint break module internal clock system integration module programmable timebase module monitor module serial peripheral 2-channel timer interface module 2 dual voltage low-voltage inhibit module 8-bit keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status user rom user ram ? 512 bytes monitor rom (monitor block) ? 350 bytes user rom vector space ? 36 bytes single external interrupt module porta ddra ddrc portc ddrd portd ddre porte internal bus pte4/osc1 pte3/osc2 rst (3) irq (3) interface module interrupt module computer operating properly module pta7/kbd7 ? ptb7/ad7 ptb6/ad6 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 8-bit analog-to-digital converter module ptc6 (1) ptc5 (1) ptc4 (1)(2) ptc3 (1)(2) ptc2 (1)(2) ptc1 (1)(2) ptc0 (1)(2) ptd7/t2ch1 (1) ptd6/t2ch0 (1) ptd5/t1ch1 (1) ptd4/t1ch0 (1) ptd3/spsck (1) ptd2/mosi (1) ptd1/miso (1) ptd0/ss (1) pte1/rxd pte0/txd 2-channel timer interface module 1 serial communications interface module power-on reset module memory map module configuration register 1 module security module configuration register 2 module power v ss v dd v ssa v dda 1. ports are software configurable with pullup device if input port. 2. higher current drive port pins 3. pin contains integrated pullup device monitor mode entry module ddrb portb v refh v refl pte2 generator module monitor rom (rom block) ? 649 bytes 15,872 bytes registers ? 64 bytes pta0/kbd0 (1) monitor rom (jump table) ? 24 bytes
reserved registers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 283 $0000 i/o registers 64 bytes $003f $0040 ram 512 bytes $023f $0240 unimplemented 6416 bytes $1b4f $1b50 monitor rom (rom block) 649 bytes $1dd8 $1dd9 unimplemented 41,511 bytes $bfff $c000 rom 15,872 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved (subar) $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 reserved $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and co ntrol register (brkscr) $fe0c lvi status register (lvisr) $fe0d unimplemented 3 bytes $fe0f $fe10 unimplemented 16 bytes reserved for compatibility with monitor code for a-family part $fe1f table a-2. mc68hc08gt16 memory map
mc68hc08gt16 mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 284 freescale semiconductor a.5 icg trim registers the two icg trim registers at $ff80 and $ff81 ar e masked with fixed values on the mc68hc08gt16. these are not trim values. these registers are avai lable for compatibility with the mc68hc908gt16 only. on the mc68hc908gt16, these two trim regist ers are used to store user trim values. a.6 monitor rom the monitor program on the mc68hc08gt16 is for device testing only. a.7 adc reference pins (v refh and v refl ) v refh must be connected to the same voltage potential as the analog supply pin, v dda . v refl must be connected to the same voltage potential as the analog supply pin, v ssa . a.8 electrical specifications electrical specifications for the mc68hc908gt 16 apply to the mc68hc08gt16, except for the parameters indicated below. $fe20 monitor rom (monitor block) 350 bytes $ff7d $ff7e reserved $ff7f monitor rom (jump table) 1 byte $ff80 icg trim register 5v (icgtr5) fix value $ff81 icg trim register 3v (icgtr3) fix value $ff82 monitor rom (jump table) 21 bytes $ff96 $ff97 unimplemented 69 bytes $ffdb $ffdc rom vectors 36 bytes $ffff (1) 1. $fff6?$fffd reserved for eight security bytes table a-2. mc68hc08gt16 memory map (continued)
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 285 a.8.1 5.0-v dc elect rical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?2.0 ma) all i/o pins (i load = ?10.0 ma) all i/o pins (i load = ?20.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.8 v dd ? 1.5 v dd ? 1.5 ? ? ? ? ? ? ? ? ? ? ? ? 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 20ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.4 1.5 1.5 50 50 100 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ?v dd v input low voltage all ports, irq , rst , osc1 v il v ss ?0.2 v dd v dc injection current, all ports (3) 3. some disturbance of the adc accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. this parameter is guaranteed by characterization. i inj ? 2.0 ? + 2.0 ma total dc current injection (sum of all i/o) (3) i injtot ? 25 ? +25 ma i/o ports hi-z leakage current (4) 4. pullups and pulldowns are disabled. port b leakage is specified in 20.16 adc characteristics . i il ?? 10 a input current i in ?? 1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 30 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 3.90 4.25 4.50 v low-voltage inhibit, trip rising voltage v tripr 4.00 4.35 4.60 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?100 ?mv por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0 ? 100 mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0700?mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.035 ? ? v/ms
mc68hc08gt16 mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 286 freescale semiconductor a.8.2 3.0-v dc elect rical characteristics characteristic (1) 1. v dd = 3.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?0.6 ma) all i/o pins (i load = ?4.0 ma) all i/o pins (i load = ?10.0 ma) pins ptc0?ptc4 only maximum combined i oh for port c, port e, port ptd0?ptd3 maximum combined i oh for port ptd4?ptd7, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.3 v dd ? 1.0 v dd ?1.0 ? ? ? ? ? ? ? ? ? ? ? ? 30 30 60 v v v ma ma ma output low voltage (i load = 0.5 ma) all i/o pins (i load = 5.0 ma) all i/o pins (i load = 10.0 ma) pins ptc0?ptc4 only maximum combined i ol for port c, port e, port ptd0?ptd3 maximum combined i ol for port ptd4?ptd7, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.3 1.0 1.0 30 30 60 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ?v dd v input low voltage all ports, irq , rst , osc1 v il v ss ?0.3 v dd v dc injection current, all ports (3) 3. some disturbance of the adc accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. this parameter is guaranteed by characterization. i inj ? 2.0 ? + 2.0 ma total dc current injection (sum of all i/o) (3) i injtot ? 25 ? +25 ma i/o ports hi-z leakage current (4) 4. pullups and pulldowns are disabled. i il ?? 10 a input current i in ?? 1 a pullup resistors (as input only) ports pta7/kbd7 ?pta0/kbd0 , ptc6?ptc0, ptd7/t2ch1?ptd0/ss r pu 20 30 65 k capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ? v dd + 4.0 v low-voltage inhibit, trip falling voltage v tripf 2.40 2.55 2.70 v low-voltage inhibit, trip rising voltage v tripr 2.50 2.65 2.80 v low-voltage inhibit reset/recover hysteresis (v tripf + v hys = v tripr ) v hys ?60 ?mv por rearm voltage (5) 5. maximum is highest vo ltage that por is guaranteed. v por 0 ? 100 mv por reset voltage (6) 6. maximum is highest vo ltage that por is possible. v porrst 0700?mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.02 ? ? v/ms
electrical specifications mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 287 a.8.3 supply current characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted. voltage bus frequency (mhz) symbol typ (2) 2. typical values reflect average measurements at 25 c only. max unit run mode v dd supply current (3) 3. run (operating) i dd measured using external square wave clock source (f osc = 32 mhz for 5 v and f osc =16mhz for 3 v). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. measured with all modules enabled. 5.0 3.0 8 4 r idd 15 4.5 20 8 ma wait mode v dd supply current (4) 4. wait i dd measured using external square wave clock source (f osc = 32 mhz for 5 v and f osc = 16 mhz for 3 v). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. all ports configured as inputs. measured with icg and lvi enabled. 5.0 3.0 8 4 w idd 4 1.5 8 4 ma stop mode v dd supply current (5) 25c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) 5. stop i dd is measured with osc1 = v ss . 6. stop i dd with tbm enabled is measured using an external square wave clock source (f osc = 32 mhz for 5 v and f osc =16mhz for 3 v). 5.0 s idd 1 20 300 50 500 5 ? ? ? ? a stop mode v dd supply current (5) 25c 25 c with tbm enabled (6) 25 c with lvi and tbm enabled (6) ?40 c to 85 c with tbm enabled (6) ?40 c to 85 c with lvi and tbm enabled (6) 3.0 s idd 1 12 200 30 300 3 ? ? ? ? a
mc68hc08gt16 mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 288 freescale semiconductor a.9 adc characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, v dda = 5.0 vdc 10%, v ssa = 0 vdc, v refh = 5.0 vdc 10%, v refl = 0 symbol min max unit comments supply voltage v dda 2.7 (v dd min) 5.5 (v dd max) v v dda should be tied to the same potential as v dd via separate traces. input voltages v adin 0v dda v resolution b ad 88b i t s absolute accuracy (v refl = v ssa , v refh = v dda ) a ad ? 1.5 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v refl v refh vv ssa v adin v dda power-up time t adpu 16 t aic cycles adc voltage reference high v refh v ssa ? 0.1 v dda + 0.1 v v refl v refh adc voltage reference low v refl v ssa ? 0.1 v dda + 0.1 v v refl v refh conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k adversely affect internal rc charging time during input sampling. t ads 5?t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 01 hex v in = v refl full-scale reading (3) f adi fe ff hex v in = v refh input capacitance c adi ? 8 pf not tested input leakage (4) port b 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a
order numbers mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 freescale semiconductor 289 a.9.1 internal oscill ator characteristics a.9.2 memory characteristics a.10 order numbers these part numbers are generic numbers only. to pl ace an order, rom code must be submitted to the rom processing center (rpc). characteristic (1) 1. v dd = 5.5 vdc to 2.7 vdc, v ss = 0 vdc, t a = t a (min) to t a (max), unless otherwise noted symbol min typ max unit internal oscillator base frequency (2), (3) 2. internal oscillator is selectable through software for a maximum frequency. actual frequency will be multiplier (n) x base frequency. 3. f bus = (f intosc / 4) x n when internal clock source selected f intosc 183.75 245 306.25 khz internal oscillator tolerance f osc_tol ?25 ? +25 % internal oscillator multiplier (4) 4. multiplier must be chosen to limit the maximum bus frequency of 4 mhz for 2.7-v operation and 8 mhz for 4.5-v operation. n1?1 2 7? characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v note: since mc68hc08gt16 is a rom device, flash memory electrical characteristics do not apply. mc order number package operating temperature range rohs compliant mc08gt16cbe 42-pin sdip ?40 to +85 cy e s mc08gt16cfbe 44-pin qfp ?40 to +85 cy e s
mc68hc08gt16 mc68hc908gt16 ? mc68hc908gt8 ? mc68 hc08gt16 data sheet, rev. 5.0 290 freescale semiconductor

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